Studies on High-Speed Encryption-/Signature-Schemes Based on Obscure Representations

该项目是在1985-1986财政年度为开发和实现高速加密/签名系统而实施的。1)提出了一种新的非对称双射密码体制C(m，n)，它是一种以多元多项式元组为公钥的非对称双射密码体制。系统C(m，n)是由我们对函数的“模糊表示”的深入研究而产生的“算法合成法”构造的。最大的优势之一是它的处理速度。这是因为它的结构适合于高度并行处理。C(m，n)的安全性本质上取决于求解与其公钥对应的多元代数方程组的难度。2)我们利用正规基乘法器、流水线和阵列结构等多种技术开发了一套计算C(m，n)的算法。用面向并行处理的程序设计语言occam2对算法进行了描述。3)通过在一台由10台Transputer组成的机器上实现这些算法的实验，我们证实了C(m，n)的高速特性。这里，Transputer是一个通用的32位微处理器，与其他微处理器之间有四条通信链路。在一个527位的分组密码体制C(31，17)中，我们的实验表明公开的-[秘密-，分别是.]变换运行约8.1kbps[分别为4.6kbps]。4)最后，通过对上述理论和实验经验的评估，我们提出了C(m，n)的实际实现的一些基本要求。特别是，我们设计了一种硬件架构，可以在相对较小的硬件规模下实现约1 Mbps的速度。

This project was performed during the 1985-1986 fiscal years for developing and realizing a high-speed encryption/signature system. We have obtained the following results:1) We have proposed a novel asymmetric cryptosystem C(m,n), which is a kind of asymmetric bijective cryptosystems and has multivariate-polynomial-tuples as its public keys. The system C(m,n) is constructed by the "algorithm composition method" born from our deep study on the "obscure representations" of functions. One of the greatest advantages is its processing speed. This comes from the fact that its structure is suitable for highly parallel processing. The security of C(m,n) is essentially determined by the difficulty of solving a system of multivariate algebraic equations corresponding to its public key.2) We have developed a set of algorithms for C(m,n) using several techniques including the normal basis multiplier, pipeline and array architectures. The algorithms are described in occam2, a programming language oriented to parallel processing.3) By some experiments of implementing these algorithms on a machine consists of 10 transputers, we have confirmed the high-speed nature of C(m,n). Here, a transputer is a general-purpose 32-bit microprocessor having four communication links to others. In a 527-bit block cryptosystem C(31,17), our experiments shows that the public- [secret-, resp.] transformation runs about 8.1 kbps [4.6 kbps, resp.].4) Finally, by evaluating the above theoretical and experimental experiences, we have proposed some essential requirements for the practical realization of C(m,n). In particular, we have designed a hardware architecture which can be expected to achieve around 1 Mbps with relatively small scale hardware.