Design and Architecture for Racetrack based Hybrid Memory Systems

基于赛道的混合内存系统的设计和架构

• 批准号: 437232907
• 负责人: Dr.-Ing. Fazal Hameed
• 金额: --
• 依托单位: Center for Advancing Electronics Dresden (cfaed)
• 依托单位国家: 德国
• 项目类别: Research Fellowships
• 财政年份: 2020
• 资助国家: 德国
• 起止时间: 2019-12-31 至 2021-12-31
• 项目状态: 已结题
• 来源: https://gepris.dfg.de/gepris/projekt/437232907?language=en
• 关键词: Design; Architecture; Racetrack; based; Hybrid

The increasing memory capacity requirements along with the quest for high performance and low energy have made the memory system design extremely difficult. The conventional DRAM memory has reached its fundamental and physical limitation that likely prevents it from growing in capacity. The recently proposed spin-orbitronics based RaceTrack Memory (RTM) is a novel memory-storage technology that accesses and stores binary data on nanoscale magnetic wires allowing exorbitant density as well as the ability to overcome the technology scaling limitations. Despite key technological advancements, the access latency and energy consumption of RTM is highly influenced by the number of shift operations. These operations are required to move bits to the right positions in the racetracks. To enable adoption of RTM, this proposal envisions a hybrid memory system by combining RTM with DRAM and Spin Transfer Torque (STT) memories at different levels in the memory hierarchy.The hybrid memory system not only offers huge opportunities but also presents daunting challenges to handle large set of data. These systems need to adapt to the application’s diverse memory access patterns, and at the same time they need to avoid the inherent limitations of individual memories constituting them. This requires a radical shift in the memory system design and a need to revisit data management strategies at hardware and operating system level.The overall goal of this proposal is to lay the foundation for highly efficient data management on hybrid memory system. We will achieve this goal by enabling hardware and operating system joint optimizations so that applications can exploit the inherent potential of the envisioned hybrid memory system despite the extra complexity brought in by heterogeneity. Concretely, we will work on design of relatively newer RTM and its adaptation, on RTM controller design, on data classification and analysis, on hierarchy adaptation, and on system-wide data management. We will follow a co-design methodology as a way to bridge the gap between hardware and operating system layers that is greatly enlarged by the high disruption potential of hybrid memory system. On the hardware side, we will deeply investigate the architecture of the RTM to enable its efficient integration with other memories. By leveraging hardware performance monitors and intelligent controllers, we will fully describe different properties of application data and memory behavior. This will guide the hardware and the operating system (OS) to take appropriate data mapping, data remapping, RTM adaptation, and hierarchy adaptation decisions. We envisage HW-OS collaborative mechanisms to continuously adapt to the change in application data behavior and system load. This project will thus contribute to mitigate the gap between the hardware and operating system layers, enabling efficient integration of relative newer RTM with well-established memory technologies.

沿着对高性能和低能耗的追求的不断增加的存储器容量要求已经使得存储器系统设计变得极其困难。传统的DRAM存储器已经达到了其基本的和物理的限制，这可能会阻止其容量的增长。最近提出的基于自旋轨道电子学的RaceTrack存储器（RTM）是一种新颖的存储器存储技术，其在纳米级磁线上访问和存储二进制数据，从而允许过高的密度以及克服技术缩放限制的能力。 尽管取得了关键技术进步，但RTM的访问延迟和能耗仍受到轮班操作数量的高度影响。需要这些操作来将比特移动到轨道中的正确位置。 为了使RTM能够被采用，该提议设想了一种混合存储器系统，该混合存储器系统通过将RTM与DRAM和自旋转移力矩（STT）存储器在存储器层级中的不同级别相结合来实现。该混合存储器系统不仅提供了巨大的机会，而且还提出了处理大数据集的艰巨挑战。 这些系统需要适应应用程序的不同内存访问模式，同时它们需要避免构成它们的单个内存的固有限制。这就需要在存储系统的设计和需要从硬件和操作系统的层面重新审视数据管理策略的根本转变。本提案的总体目标是为混合存储系统的高效数据管理奠定基础。 我们将实现这一目标，使硬件和操作系统的联合优化，使应用程序可以利用所设想的混合存储器系统的固有潜力，尽管额外的复杂性所带来的异质性。具体而言，我们将致力于设计相对较新的RTM及其适应，RTM控制器设计，数据分类和分析，层次结构的适应，以及系统范围内的数据管理。 我们将遵循协同设计的方法，作为一种方式来弥合硬件和操作系统层之间的差距，这是大大扩大了混合存储系统的高破坏潜力。 在硬件方面，我们将深入研究RTM的体系结构，使其与其他存储器的有效集成。 通过利用硬件性能监视器和智能控制器，我们将充分描述应用程序数据和内存行为的不同属性。 这将指导硬件和操作系统（OS）采取适当的数据映射、数据重映射、RTM适配和层次结构适配决策。我们设想HW-OS协作机制，以不断适应应用程序数据行为和系统负载的变化。因此，该项目将有助于缓解硬件和操作系统层之间的差距，使相对较新的RTM与成熟的内存技术的有效集成。

项目成果

ROLLED: Racetrack Memory Optimized Linear Layout and Efficient Decomposition of Decision Trees

• DOI: 10.1109/tc.2022.3197094
• 发表时间: 2023-05
• 期刊: IEEE Transactions on Computers
• 影响因子: 3.7
• 作者: Christian Hakert;Asif Ali Khan;Kuan-Hsun Chen;F. Hameed;J. Castrillón;Jian-Jia Chen

DNA Pre-Alignment Filter Using Processing Near Racetrack Memory

使用近赛道内存处理的 DNA 预对准过滤器

• DOI: 10.1109/lca.2022.3194263
• 期刊: IEEE Computer Architecture Letters
• 影响因子: 2.3
• 作者: F. Hameed;A.A. Khan;S. Olliver;A.K. Jones;J. Castrillon
• 通讯作者: J. Castrillon

BlendCache: An Energy and Area Efficient Racetrack Last-Level-Cache Architecture

BlendCache：能源和面积高效的赛道末级缓存架构

• DOI: 10.1109/tcad.2022.3161198
• 期刊: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
• 影响因子: 2.9
• 作者: F. Hameed;J. Castrillon
• 通讯作者: J. Castrillon

ALPHA: A Novel Algorithm-Hardware Co-Design for Accelerating DNA Seed Location Filtering

ALPHA：一种加速 DNA 种子位置过滤的新型算法-硬件协同设计

• DOI: 10.1109/tetc.2021.3093840
• 期刊: IEEE Transactions on Emerging Topics in Computing
• 影响因子: 5.9
• 作者: F. Hameed;A.A. Khan;J. Castrillon
• 通讯作者: J. Castrillon