Universal Memcomputing in Hardware Realizations of Memristor Cellular Nonlinear Networks

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In Mem2CNN phase II, we intend to expand the incorporation of memristor devices and their unique properties into Memristive Cellular Neural Networks (M-CNNs) beyond their current application solely within the cell state component. The ultimate objective of the proposed project is to explore and implement novel hardware of a universal non-von Neumann computing architecture with stored programmability that will materialize the M-CNN Universal Machine (M-CNNUM). In the proposed system, memristor devices arranged in crossbars will be utilized to implement a M-CNN gene family, the so-called Chromosome. In CNN theory, chromosomes are collections of CNN genes that are executed in a sequential manner to carry out diverse computational tasks, akin to the algorithmic operations observed in traditional computer systems. Memristor crossbar arrays can be utilized as dot-product engines, implementing the necessary multiply-and-accumulate operations for the calculation of each cell’s offset, which resembles the aggregate contribution of neighboring cells’ input, and output, and the fixed bias, weighted by each gene’s synaptic weights. Then, we plan to combine this novel chromosome memristor-based hardware realization with the rich dynamics of the M-CNN core, which offers both local nonvolatile memory and memcomputing capabilities, to design the whole M-CNNUM cell and demonstrate the execution of M-CNNUM instructions on our proposed hardware. In order to facilitate the system development, it is essential to employ mixed-signal design techniques, exploiting the compact and energy-efficient analog computing cores, accompanied by the required digital control circuitry in the peripheral regions that are managing system’s operation and data transfer. This design, which will enable the execution of M-CNNUM operations in a massively parallel manner, achieving high speed universal computation with low energy budget requirements, has to incorporate all the potential circuit imperfections of CMOS/Memristor fabricated circuits. Additionally, it necessitates the development of innovative techniques for the design of the novel M-CNNUM microarchitecture, which resembles the internal design and organization of this novel computer. Last but not least, we envisage the establishment of a software simulation infrastructure that will accurately describe the operation of the proposed M-CNNUM hardware and will be used to demonstrate the proper operation of the proposed M-CNNUM system in real-life tasks, e.g., image processing applications. As well as a physical realization of a small-scale functional M-CNNUM array, for the proof-of-concept, is planned. Summarizing, the main objectives of Mem2CNN Phase II are the following: 1. Derive a crossbar-based M-CNNUM chromosome structure, 2. Demonstrate the operation of M-CNNUM instructions on our hardware, 3. Realization of a M-CNNUM microarchitecture, 4. Proof-of-concept application of the developed M-CNNUM implementation.