Neurotransistor-based Memristive Crossbar Memcomputing (NeuroMCross)

点击翻译按钮获取中文摘要

Brain-inspired Spiking Neural Networks (SNNs) operate in parallel and asynchronously via spatio-temporal spikings of interconnected neurons. Capacitive neural networks that charge and discharge capacitive mem-elements, resulting in the removal or return of energy from/to the signal sources, can lead to considerably lower energy consumption in comparison to conventional artificial neural network (ANN) structures performing massively matrix-vector multiplications. In this regards memtransistor neurons combining memristive/memcapacitive devices and transistor structures can enable fundamental features of neurons like the leaky-integrate-and-fire (LIF) behavior. This can be built into a neuromorphic memcomputing building block for versatile SNN architectures. In this project we aim at the development of a novel neuro-crossbar structure, which combines and extends the functionalities of the individual components of the memristive/memcapacitive crossbar and neurotransistor based on Al2O3/Nb2O5 devices developed in the preceding BioMCross project. Unlike previous memtransistor approaches, we fabricate an integrated multi-input memcapacitive crossbar structure at the gate of a silicon-based n-channel field effect transistor (nFET), which is able to create a controlled 1D and 2D percolation path along the transistor channel. The LIF neuro-crossbar integrates high complexity, such as a fully connected layer for multiple inputs, an all-or-nothing feature extraction for 1D percolation or OR-linked 2D percolation paths as well as recurrent connection in a single device structure. For this purpose, the proposed work will cover several essential aspects: (i) the neuro-crossbar device modeling using 3D TCAD simulation, (ii) the neuro-crossbar fabrication and parameter optimization by integration of multiple Al2O3/Nb2O5 memristive/memcapacitive devices on top of the transistor structure, (iii) the neuro-crossbar circuit system modeling and analysis of read/write operation and (iv) the design of temporal coded signals for recurrent SNNs, hardware-aware offline training, performance optimization as well as implementation of local learning rules. Finally, we will investigate various time series datasets to demonstrate the realization of recurrent SNNs interconnected neuro-crossbar structures and evaluate the system's performance compared to conventional CMOS-based SNN and purely memristive ANN accelerator systems. This research aims to extend the state of the art by a new neuro-crossbar building block and to provide a comprehensive understanding of the feasibility of practical realization of memcapacitive SNN systems based on highly integrated device concepts.