A Multithreaded Ultra-pipelined Processor Architecture

随着金属氧化物半导体（MOS）器件尺寸按比例缩小，MOS晶体管的开关延迟时间与比例因子成正比减小。因此，随着精密加工技术的进步，工作频率也在不断提高。然而，由于电磁学的规律，布线延迟时间对于标度规则是不变的。即接线电阻与比例因子成反比增大，而接线电容则与比例因子成反比减小。因此，当制造工艺技术变得极其精细时，很难提高处理器芯片的工作频率。为了克服这种情况，研究了多线程管道体系结构和母管道原理。多线程架构的处理器将指令从彼此独立的不同指令流中放入管道中。因此，当应用程序被分解为许多独立的线程时，该体系结构可以实现更深入的管道化。当处理器工作在波管道原理下时，可以打破切换和传播延迟的限制，因为时钟周期是由管道级最大和最小路径延迟之差决定的。本文对波式流水线多线程处理器的设计方法进行了研究，特别是在引入波式流水线的情况下，考虑布线长度和低功耗设计的延迟平衡方法。本报告由以下八个部分组成。一个多线程流水线处理器的性能用于多线程流水线处理器的流水线式缓存存储器。波浪管道延迟平衡方法的改进。可变线程数处理器的评估。布线结构的优化。一种用于多线程处理器的高吞吐量存储系统设计。对延迟平衡方法进行了进一步改进。波浪流水线处理器的低功耗设计。少

As shrinking the dimension of Metal Oxide Semiconductor (MOS) devices according to the scaling down rule, the switching delay time of MOS transistor decreases in proportional to the scaling factor. So, the operating frequency goes up relying upon progress of the fine fabrication process technology.However, the wiring delay time is invariable for the scaling rule because of a law of electromagnetism. That is, the wiring resistance increases in inverse proportion to scaling factor while the wiring capacitance decreases in proportion to scaling factor. Therefore, when the fabrication process technology becomes extremely fine, it is difficult to increase the operating frequency of the processor chip.In order to overcome that situation, the multithreaded pipeline architecture and the wive pipeline principle are investigated.A processor of multithreaded architecture puts instructions into a pipeline from distinct instruction streams independent each other. So, the architecture enables the ex … More treme deep pipelining if the application program is decomposed to a lot of independent threads.When a processor operates in the wave pipeline principle, it can break the limit of switching and propagation delays, because the clock period is determined with the difference between maximum and minimum path delay of pipeline stages.The authors are investigating design methodologies of the wave pipelining multithreaded processors, especially, the delay balancing method considering wiring length and low power consumption design if introducing wave pipelining.The report consists of the following eight parts.1. Performance of a multithreaded pipeline processor.2. A pipelined cache memory for multithreaded pipeline processors.3. Improvement of a delay balancing method for wave pipelining.4. Evaluation of a variable thread number processor.5. Optimization of wiring structures.6. A high throughput memory system design for a multithreaded processor.7. More improvement for delay balancing method.8. A low power consumption design for wave pipelining processors. Less