A study on high-speed A/D converters for vision system LSIs

点击翻译按钮获取中文摘要

Vision chips that integrate parallel image processing engines are essential devices for the applications of robotics, FA, ITS and so on. The bottle neck in such applications lies in the analog-to-digital conversion to transfer the data from image acquisition device to the processor. In the conventional method of A/D converters integrated on image sensors, the A/D converter has to be implemented in a small size, and hence the relatively slow speed A/D converters are used. This restricts the total frame rate of the image acquisition. The head investigator of this project has developed a method to implement a high-speed A/D converter in a reduced area by using correlation properties of moving pictures. The number of comparators is reduced to be 1/4 and 1/6 for 8 bit and 10 bit cases, respectively. As the basic topology for the A/D converter array for high-speed image sensors, we propose a pipeline A/D conversion technique, and a synchronized read out method of signals from the sensor array with 100% efficiency. A 10bit 20Msamples/s A/D converter has been implemented using 0.6μm CMOS technology. The non-linearity error was less than 0.6LSB.The 8bit 10 M samples/s version using simple cascode amplifiers to integrate it on high-speed image sensors is designed and in under fabrication. The 128-channel A/D converter array can be integrated on a CMOS image sensor with 512 x 512 pixels and the resulting area of A/D converter array is estimated to be 6.9 x 1.5 mm^2. The estimated frame speed is 10000frames/s. The use of electronic shutter function and the implementation of the high-speed image sensor integrating the A/D converter array are left as near future subject.