Study on speculative parallel architecture using runtime program restructuring

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The speculative parallel architecture utilizing on-chip resources is proposed. The proposed architecture, Runtime Restructuring extracts parallelism dynamically at runtime from a sequential binary program. In order to reduce overheads associated with frequent fork/join and frequent register-to- register communication in existing thread-level speculative architecture, Runtime Restructuring modifies a sequential binary program to a speculative SPMD program with duplicated execution.Since generation of control flow is influenced by the history of past execution, its parallelization is necessary to achieve the accurate execution status. Then we introduce a binary translation method to reduce overheads for analyzing parallel constructs and register dependency. We show the details of the parallel formation of control flow, and the evaluation results on SPEC benchmarks. Tomcatv gets 3.9 times and compress gets significant performance gain on 4CPUs. On SPEC INT benchmarks, binary translation is useful to reduce overheads in short loops.