Double Relaxation Oscillation SQUID Magnetometer with Superconducting Digital Flux-Locked Loop

具有超导数字锁磁环的双弛豫振荡 SQUID 磁力计

• 批准号: 14350177
• 负责人: MYOREN Hiroaki
• 金额: $ 5.63万
• 依托单位: Saitama University
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for Scientific Research (B)
• 财政年份: 2002
• 资助国家: 日本
• 起止时间: 2002 至 2004
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/en/grant/KAKENHI-PROJECT-14350177/
• 关键词: Double Relaxation Oscillation SQUID; Flux Locked-Loop; Superconducting Latching Logic; Single Flux Quantum Logic Circuits; Up; Down Counter; D; A Converter; 2-Phase Power Supply; Cell Library; 単一磁束量子論理回路

On-chip double relaxation oscillation SQUID(DROS) with a superconducting digital flux locked-loop(FLL) circuit is demonstrated far high sensitive magnetic flux sensor and SQUID amplifier. In this study, we examined two kinds of superconducting digital FLL circuits : one was composed of a 8-bit up/down counter and a 8-bit R-2R ladder-type D/A converter designed using 4JL-gates which are driven by a two phase power supply at a frequency up to 4GHz. The other one was composed of an on-chip FLL circuit based on a Josephson counter and a 6-bit up/down counter using SFQ logic gates.In the up/down counter, we used binary carry lookahead(BCL) circuits for high-speed operation. Logic simulations for the 4JL 8-bit up/down counter with BCL circuits showed correct up-and down-counting operation at 4GHz clock frequency assuming a 2.5kA/cm^2 Nb/Al-AlO_x/Nb junction technology. We expected that a DROS with the superconducting digital FLL circuit has large slew rate as high as 10-7Φ_0/s.Using the 6-bit up/down counter using SFQ logic gates, logic simulations showed the correct up and down counting operation up to 33GHz and we expected that a DROS with the SFQ digital FLL circuits can be operated at 10GHz.

介绍了一种采用超导数字锁磁环(FLL)电路的片上双弛豫振荡SQUID(DROS)，它具有极高灵敏度的磁通传感器和SQUID放大器。在这项研究中，我们研究了两种超导数字FLL电路：一种是由一个8位加/减计数器和一个8位R-2R梯形D/A转换器组成的，该D/A转换器采用4JL门，由频率高达4 GHz的两相电源驱动。另一种由基于约瑟夫森计数器的片上FLL电路和采用SFQ逻辑门的6位加/减计数器组成，加/减计数器采用二进制超前进位(BCL)电路进行高速运算。采用BCL电路的4JL 8位加/减计数器的逻辑模拟表明，假设采用2.5kA/cm2Nb/Al-AlOx/Nb结工艺，4 GHz时钟频率下的加/减计数操作是正确的。我们预计超导数字锁相环电路的DROS具有高达10-7Φ_0/s的大转换速率。使用6位加/减计数器，逻辑模拟表明，在高达33 GHz的频率范围内，正确的加/减计数操作，我们预计具有超导数字锁相环电路的DROS可以在10 GHz下工作。

项目成果

Myoren H. et al.: "Design of single-flux-quantum universal gates with a wide operating margin"Supercond.Sci.Technol.. 16. 1447-1451 (2003)

Myoren H. 等人：“具有宽操作裕度的单通量量子通用门的设计”Supercond.Sci.Technol.. 16. 1447-1451 (2003)

Design of single-flux-quantum universal gates with a wide operating margin

具有较宽运行裕度的单通量量子通用门的设计

• 发表时间: 2003
• 期刊: Supercond.Sci.Technol. 16
• 作者: K.T.Liu;Y.K.Su;S.J.Chang;K.Onomitsu;Y.Horikoshi;Myoren H.et al.
• 通讯作者: Myoren H.et al.

Double Relaxation Oscillation SQUID with a 4JL On-Chip Digital Flux Locked-Loop Circuit

具有 4JL 片上数字磁通锁环电路的双弛豫振荡 SQUID

• 发表时间: 2005
• 期刊: IEEE Trans.Appl.Supercond. 15(in press)
• 作者: T.Tanaka;G.C.Montanari;R.Muelhaupt;Katsuyasu Nakano;Myoren H.et al.
• 通讯作者: Myoren H.et al.

High Reliable Fabrication Process for Superconducting Integrated Circuits with Simply Fabrication Technology of All Various Via-holes Using Photosensitive Polyimide Insulation Layers

光敏聚酰亚胺绝缘层各种过孔简单制作技术的高可靠超导集成电路制作工艺

• 发表时间: 2005
• 期刊: IEEE Trans.Appl.Supercond. 15(in press)
• 作者: M.Fujita;N.Kawamoto;M.Sasajima;Y.Horikoshi;M.Takezawa;Kikkuchi K.et al.
• 通讯作者: Kikkuchi K.et al.