Study on the Novel Single-Quantum Processing System using Single-Flux-Quantum Logic Circuits
Study on the Novel Single-Quantum Processing System using Single-Flux-Quantum Logic Circuits
批准号:
12450144
负责人:
YOSHIKAWA Nobuyuki
金额:
$9.6万
依托单位国家:
日本
项目类别:
Grant-in-Aid for Scientific Research (B)
财政年份:
2000
资助国家:
日本
项目状态:
已结题
起止时间:
2000 至 2002
中文摘要
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英文摘要
Single-flux-quantum (SFQ) logic circuits, which utilize an SFQ pulse in the superconducting circuits as a logical bit information, attract a great deal of attention recently because of their high-speed operating speed and low power dissipation compared with the semiconductor integrated circuits. Because the logical bit information in the SFQ circuits is represented by an SFQ, which is considered as a particle, we may build up a new type of logic operation system different from the conventional logic using me Boolean function.The purpose of this study is to realize a single-quantum integrated system through the consideration of new SFQ logic circuits using a binary decision diagram (BDD), which is one kind of directional graphs.In the research of 2001, we have optimized circuit parameters of the basic circuit cells for the BDD SFQ logic circuits and verified their operations. In 2002 we have designed and implemented the microprocessor components and investigated their functions in order to build a large-scale BDD SFQ logic circuit system. In 2003 we have designed the SFQ microprocessor prototype to investigate the feasibility of a large SFQ circuit system based on the asynchronous circuit design approach. The SFQ microprocessor designed is 8-bit bit-serial microprocessor having seven instructions. Its target clock frequency is 16 GHz. We have successfully confirmed the correct operations in all the circuit components, including register files, an ALU, a program counter and a controller.These results show the feasibility of a large-scale SFQ logic circuit system as a high-end computing system in the next generation.
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吉川信行,森静香,越山潤一: "Verilog HDLによるRSFQ論理回路のタイミング設計手法の検討"電子情報通信学会論文誌C. 7. 643-650 (2000)
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J.Koshiyama, N.Yoshikawa: "A Cell-Based Design Approach for RSFQ Circuits Based on Binary Decision Diagram"IEEE Trans. Appl. Superconductivity. Vol.11. 263-266 (2001)
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N.Yoshikawa, J.Koshiyama, K.Motoori, F.Matsuzaki, K.Yoda: "Cell-based top-down design methodology for RSFQ digital circuits"Physica C. 357-360. 1529-1539 (2001)
N.Yoshikawa、J.Koshiyama、K.Motoori、F.Matsuzaki、K.Yoda:“RSFQ 数字电路的基于单元的自顶向下设计方法”Physica C. 357-360。
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K.Fujiwara, H.Hoshina, J.Koshiyama, N.Yoshikawa: "Design and Component Test of RSFQ Packet Decoders for Shift Register Memories"Physica C. 378-381. 1475-1480 (2002)
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N. Yoshikawa and J. Koshiyama: "Top-Down RSFQ Logic Design Based on a Binary Decision Diagram"IEEE Trans. Appl. Superconductivity. 11. 1098-1101 (2001)
N. Yoshikawa 和 J. Koshiyama:“基于二元决策图的自顶向下 RSFQ 逻辑设计”IEEE Trans。
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