Highly Parallel Network Processor Based on Self Timed Pipeline Circuit

本课题的研究目标是充分利用自定时流水线作为一种低功耗、易设计、高性能的电路，建立一个灵活的高集成度的网络处理器滴漏架构。该项目的一部分是通过开发和评估新设计的大规模集成电路来进行的。本项目将提出的体系结构应用于Diffserv等基于类的QoS控制功能和防火墙、入侵检测系统（IOS） 1等高级包过滤，获得了以下基础研究成果自定时优先级排队机制我们提出了一种自定时优先级排队机制，在该机制中，折叠管道的每一对级都有一个旁路级，以最小化排队延迟时间。我们观察到，采用0.18 um CMOS工艺制作的测试芯片可以在8个不同的类别下实现大约100 M的IP数据包/s高速包过滤的数据驱动实现我们提出了两种数据驱动实现，一种是第4层包头的静态过滤，另一种是有效载荷检测的签名匹配。我们的评估结果表明，仅在一个日期驱动处理器上，静态过滤可以达到4 M数据包/s，签名匹配可以达到0.1 M数据包/s。通过在FPGA上实现自定时数据驱动处理器，评估了静态滤波专用指令的额外电路开销。结果表明，只需增加6%的栅极就足以实现所提出的结构自定时管道系统的性能估计模型我们建立了一个宏流模型，通过该模型可以简单地模拟自定时管道中每个数据包的流动行为。利用该模型，可以将自定时管道系统的仿真时间缩短一半，并且具有较好的精度。

The objectives of this research project is to establish a flexible architecture of highly integrated network processor drip by exhaustively utilizing the self-timed pipeline as one of low-power, easily designed and high performance circuits. A part of the project has been conducted through developing and evaluating a newly designed LSI. The following basic research results have been obtained in this Project by applying the proposed architecture to the class based QoS control function like Diffserv and the high-level packet filtering such as that of firewall and intruder detection systam (IOS).1 Self-Timed priocity queueing mechanismWe proposed a self-timed priority queueing mechanism in which every pair of stage of a folded pipeline has a bypass stage to minimize queueing delay time. We observed that the test chip fabricated by 0.18 um CMOS process could achieve around 100 M IP packets/s with 8 different classes.2 Data-driven implementation of high-speed packet filteringWe proposed two data-driven implementations one is a static filtering of layer 4 packet header and the other one is a signature matching for payload inspection. Our evaluation results showed that 4 M packets/s for the static filtering and 0.1 M packets/s for the signature matching could be achieved on only one date-driven processor. Additional circuit cost of some dedicated instructions for the static filtering was evaluated by implementing a self-timed data-driven processor on FPGA. The result indicated that only 6 % increase of gates was enough to realize the proposed architecture.3 Performance estimation model of the self-timed pipelined systemsWe formulated a macro flow model by which the behavior of ever packet flowing in a self-timed pipeline can be modeled simply. Using this model, we can reduce simulation time of the self-timed pipelined systems in half with reasonable accuracy in comparison to the existing naive model.