Highly Parallel Network Processor Based on Self Timed Pipeline Circuit

本研究计画的目标是建立一个高度整合的网路处理器架构，充分利用自时序管线作为一种低功率、易设计、高效能的电路。该项目的一部分已经通过开发和评估新设计的LSI进行。本项目将该体系结构应用于Diffserv等基于类的QoS控制功能和防火墙、入侵检测系统（IOS）等高级包过滤功能中，取得了以下基本研究成果：1自定时优先级搜索机制提出了一种自定时优先级搜索机制，该机制具有自适应性、自适应性等特点。定时优先级调度机制，其中折叠流水线的每一对级具有旁路级以最小化调度延迟时间。我们观察到，采用0.18 um CMOS工艺制作的测试芯片可以实现8种不同类别的约100 M IP数据包/s。2数据驱动的高速数据包过滤实现我们提出了两种数据驱动的实现方案，一种是第4层数据包报头的静态过滤，另一种是有效载荷检测的签名匹配。我们的评估结果表明，4 M包/s的静态过滤和0.1 M包/s的签名匹配可以实现只有一个日期驱动的处理器。通过在FPGA上实现自定时数据驱动处理器，评估了静态滤波专用指令的额外电路成本。结果表明，仅增加6%的门数就足以实现所提出的体系结构。3自定时流水线系统的性能评估模型我们建立了一个宏流模型，通过该模型可以简单地模拟数据包在自定时流水线中的流动行为。使用这个模型，我们可以减少一半的自定时流水线系统的仿真时间与合理的精度相比，现有的天真的模型。

The objectives of this research project is to establish a flexible architecture of highly integrated network processor drip by exhaustively utilizing the self-timed pipeline as one of low-power, easily designed and high performance circuits. A part of the project has been conducted through developing and evaluating a newly designed LSI. The following basic research results have been obtained in this Project by applying the proposed architecture to the class based QoS control function like Diffserv and the high-level packet filtering such as that of firewall and intruder detection systam (IOS).1 Self-Timed priocity queueing mechanismWe proposed a self-timed priority queueing mechanism in which every pair of stage of a folded pipeline has a bypass stage to minimize queueing delay time. We observed that the test chip fabricated by 0.18 um CMOS process could achieve around 100 M IP packets/s with 8 different classes.2 Data-driven implementation of high-speed packet filteringWe proposed two data-driven implementations one is a static filtering of layer 4 packet header and the other one is a signature matching for payload inspection. Our evaluation results showed that 4 M packets/s for the static filtering and 0.1 M packets/s for the signature matching could be achieved on only one date-driven processor. Additional circuit cost of some dedicated instructions for the static filtering was evaluated by implementing a self-timed data-driven processor on FPGA. The result indicated that only 6 % increase of gates was enough to realize the proposed architecture.3 Performance estimation model of the self-timed pipelined systemsWe formulated a macro flow model by which the behavior of ever packet flowing in a self-timed pipeline can be modeled simply. Using this model, we can reduce simulation time of the self-timed pipelined systems in half with reasonable accuracy in comparison to the existing naive model.