Highly Parallel Network Processor Based on Self Timed Pipeline Circuit

本研究项目的目的是通过充分利用自定时流水线作为一种低功耗、易设计、高性能的电路，建立一种灵活的高集成度网络处理器DRIP的体系结构。该项目的一部分是通过开发和评估新设计的大规模集成电路来进行的。通过将所提出的体系结构应用于DiffServ等基于类的服务质量控制功能和防火墙和入侵检测系统(IOS)的高级包过滤，取得了以下基础研究成果。1.自定时优先级排队机制我们提出了一种自定时优先级排队机制，其中折叠流水线的每一级都有一个旁路阶段来最小化排队延迟时间。测试结果表明，采用0.18um工艺制作的测试芯片可以实现约100M的8种不同类别的IP包/S。2.高速包过滤的数据驱动实现我们提出了两种数据驱动的实现方案，一种是对第四层包头的静态过滤，另一种是用于负载检测的签名匹配。测试结果表明，仅在一个数据驱动处理器上就可以实现静态过滤的4M包/S和签名匹配的0.1M包/S。通过在现场可编程门阵列上实现自定时数据驱动处理器，评估了一些用于静态滤波的专用指令的额外电路开销。结果表明，仅增加6%的门数就足以实现所提出的体系结构。3.自定时流水线系统的性能评估模型我们建立了一个宏流模型，利用该模型可以简单地模拟每一个分组在自定时流水线中的行为。与现有的朴素模型相比，使用该模型可以将自定时流水线系统的仿真时间减少一半，并且具有相当的精度。

The objectives of this research project is to establish a flexible architecture of highly integrated network processor drip by exhaustively utilizing the self-timed pipeline as one of low-power, easily designed and high performance circuits. A part of the project has been conducted through developing and evaluating a newly designed LSI. The following basic research results have been obtained in this Project by applying the proposed architecture to the class based QoS control function like Diffserv and the high-level packet filtering such as that of firewall and intruder detection systam (IOS).1 Self-Timed priocity queueing mechanismWe proposed a self-timed priority queueing mechanism in which every pair of stage of a folded pipeline has a bypass stage to minimize queueing delay time. We observed that the test chip fabricated by 0.18 um CMOS process could achieve around 100 M IP packets/s with 8 different classes.2 Data-driven implementation of high-speed packet filteringWe proposed two data-driven implementations one is a static filtering of layer 4 packet header and the other one is a signature matching for payload inspection. Our evaluation results showed that 4 M packets/s for the static filtering and 0.1 M packets/s for the signature matching could be achieved on only one date-driven processor. Additional circuit cost of some dedicated instructions for the static filtering was evaluated by implementing a self-timed data-driven processor on FPGA. The result indicated that only 6 % increase of gates was enough to realize the proposed architecture.3 Performance estimation model of the self-timed pipelined systemsWe formulated a macro flow model by which the behavior of ever packet flowing in a self-timed pipeline can be modeled simply. Using this model, we can reduce simulation time of the self-timed pipelined systems in half with reasonable accuracy in comparison to the existing naive model.