Asynchronous Pulse-type Chaotic Neural Networks with Hardware Models
Asynchronous Pulse-type Chaotic Neural Networks with Hardware Models
批准号:
15560308
负责人:
SAEKI Katsutoshi
金额:
$2.3万
依托单位:
依托单位国家:
日本
项目类别:
Grant-in-Aid for Scientific Research (C)
财政年份:
2003
资助国家:
日本
项目状态:
已结题
起止时间:
2003 至 2005
中文摘要
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英文摘要
Brain subsystems have a high degree of information processing ability, namely recognition and learning. However, the information processing functions have not been clarified as yet. As a result, various neuron models and artificial neural networks have been studied in order to clarify the information processing functions of biological neural networks, and apply them to engineering problems. Artificial neural networks performing similarly to the human brain are required for constructing an information processing system of brain-type using the VLSI technology.In this study, we discuss asynchronous pulse-type chaotic neural networks with hardware models.Results,(1)In our proposed hardware active dendrite model, it is shown clearly that the active dendrite model has similar biological backpropagation characteristics (References No.1).(2)We propose the CMOS implementation of a multiple valued memory cell using A-shaped negative resistance devices for plastic synapses (References No.2).(3)We construct a short-term memory circuit, and we verify the memory patterns of the temporal pattern recognition circuit using hardware ring neural networks (References No.3).(4)We investigate the effect of STDP on the ability to extract phase information buried in fluctuation. We focus on spike timing dependent synaptic plasticity (STDP), and we construct neural networks from a pulse-type hardware neuron model using STDP. We show that phase information buried in fluctuation is revealed by the effect of STDP, making it possible to decode the synaptic weight. Moreover, we show that it is possible to extract the phase difference buried in fluctuation representing the reinforcement part of the synaptic weight, using neural networks with STDP.(5)It is shown that generation and transition of oscillation patterns are possible by giving external inputs of one pulse to the CPG (Central Pattern Generator) model (References No.4).
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DOI:
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发表时间:
2003
期刊:
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Science vol. E86-A, no.9
影响因子:
--
作者:
[Zongyang Xue, Haruki Nagami, Kazutaka Someya, Yoshifumi Sekine]
通讯作者:
Yoshifumi Sekine
Katsutoshi Saeki: "CMOS Implementation of a Multiple-Valued Memory Cell Using A-Shaped Negative-Resistance Devices"IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. Vol.J87-A, no.4. (2004)
Katsutoshi Saeki:“使用 A 形负阻器件实现多值存储单元的 CMOS 实现”IEICE 电子、通信和计算机科学基础汇刊。
DOI:
--
发表时间:
期刊:
影响因子:
--
作者:
[]
通讯作者:
CMOS Implementation of a Multiple-Valued Memory Cell Using A-Shaped Negative-Resistance Devices
使用 A 形负阻器件的多值存储单元的 CMOS 实现
DOI:
--
发表时间:
2004
期刊:
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences vol.J87-A, no.4
影响因子:
--
作者:
[Katsutoshi Saeki]
通讯作者:
Katsutoshi Saeki
A Pulse-Type Hardware CPG model for Quadruped Locomotion Pattern
四足动物运动模式的脉冲型硬件CPG模型
DOI:
--
发表时间:
2006
期刊:
International Congress Series vol.1291(印刷中)
影响因子:
--
作者:
[Keiko Hata, Katsutoshi Saeki, Yoshifumi Sekine]
通讯作者:
Yoshifumi Sekine
Short-term memory circuit using hardware ring neural networks
使用硬件环形神经网络的短期记忆电路
DOI:
--
发表时间:
2005
期刊:
Artificial Life and Robotics vol.9, no.2
影响因子:
--
作者:
[Naoya Sasano, Katsutoshi Saeki, Yoshifumi Sekine]
通讯作者:
Yoshifumi Sekine
共 7 条
Development of VLSI Devices with Flexibility and Robustness
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批准号:25420344
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项目类别:Grant-in-Aid for Scientific Research (C)
-
资助金额:$3.33万
-
财政年份:2013
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负责人:SAEKI Katsutoshi
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依托单位:
Development of Neuron Device with Learning Function
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批准号:21560367
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项目类别:Grant-in-Aid for Scientific Research (C)
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资助金额:$2.91万
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财政年份:2009
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负责人:SAEKI Katsutoshi
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依托单位:
海外基金