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Asynchronous Pulse-type Chaotic Neural Networks with Hardware Models

具有硬件模型的异步脉冲型混沌神经网络

基本信息

批准号：
15560308
负责人：
SAEKI Katsutoshi
金额：
$ 2.3万
依托单位：
Nihon University
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (C)
财政年份：
2003
资助国家：
日本
起止时间：
2003 至 2005
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/en/grant/KAKENHI-PROJECT-15560308/
关键词：
Pulse-type Neuron model Negative resistance Multiple valued memory cell Hardware active dendrite model CPG model STDP Ring neural network 可塑性ニューラルネットワーク環状アナログハードウェアカオス FPGA DSP

项目摘要

Brain subsystems have a high degree of information processing ability, namely recognition and learning. However, the information processing functions have not been clarified as yet. As a result, various neuron models and artificial neural networks have been studied in order to clarify the information processing functions of biological neural networks, and apply them to engineering problems. Artificial neural networks performing similarly to the human brain are required for constructing an information processing system of brain-type using the VLSI technology.In this study, we discuss asynchronous pulse-type chaotic neural networks with hardware models.Results,(1)In our proposed hardware active dendrite model, it is shown clearly that the active dendrite model has similar biological backpropagation characteristics (References No.1).(2)We propose the CMOS implementation of a multiple valued memory cell using A-shaped negative resistance devices for plastic synapses (References No.2).(3)We construct a short-term memory circuit, and we verify the memory patterns of the temporal pattern recognition circuit using hardware ring neural networks (References No.3).(4)We investigate the effect of STDP on the ability to extract phase information buried in fluctuation. We focus on spike timing dependent synaptic plasticity (STDP), and we construct neural networks from a pulse-type hardware neuron model using STDP. We show that phase information buried in fluctuation is revealed by the effect of STDP, making it possible to decode the synaptic weight. Moreover, we show that it is possible to extract the phase difference buried in fluctuation representing the reinforcement part of the synaptic weight, using neural networks with STDP.(5)It is shown that generation and transition of oscillation patterns are possible by giving external inputs of one pulse to the CPG (Central Pattern Generator) model (References No.4).

大脑子系统具有高度的信息处理能力，即识别和学习。然而，信息处理功能尚未明确。因此，人们研究了各种神经元模型和人工神经网络，以阐明生物神经网络的信息处理功能，并将其应用于工程问题。利用超大规模集成电路（VLSI）技术构造脑型信息处理系统，需要具有类似于人脑的性能的人工神经网络，本文讨论了具有硬件模型的异步脉冲型混沌神经网络，结果表明：（1）在我们提出的硬件活性树突模型中，活性树突模型具有类似于生物学的反向传播特性（参考文献1）; (2)We提出了使用A形负电阻器件用于塑性突触的多值存储单元的CMOS实现（参考文献No.2）。(3)We构造了一个短时记忆电路，并使用硬件环神经网络验证了时间模式识别电路的记忆模式（参考文献3）。(4)We研究STDP对提取隐藏在波动中的相位信息的能力的影响。我们专注于尖峰时间依赖的突触可塑性（STDP），我们构建神经网络的脉冲型硬件神经元模型使用STDP。我们发现，相位信息埋在波动揭示了STDP的效果，使解码突触的重量。此外，我们表明，它是可能的提取相位差埋在波动代表的强化部分的突触权重，使用神经网络与STDP。(5)It通过向CPG（Central Pattern Generator）模型（参考文献No.4）提供一个脉冲的外部输入，证明了振荡模式的产生和过渡是可能的。

项目成果

期刊论文数量（15）

专著数量（0）

科研奖励数量（0）

会议论文数量（0）

专利数量（0）

A Study of Nonlinear Characteristics in a Hardware Active Dendrite Model

硬件主动树突模型非线性特性的研究

DOI：
发表时间：
2003
期刊：
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Science vol. E86-A, no.9
影响因子：
0
作者：
Zongyang Xue;Haruki Nagami;Kazutaka Someya;Yoshifumi Sekine
通讯作者：
Yoshifumi Sekine

Katsutoshi Saeki: "CMOS Implementation of a Multiple-Valued Memory Cell Using A-Shaped Negative-Resistance Devices"IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. Vol.J87-A, no.4. (2004)

Katsutoshi Saeki：“使用 A 形负阻器件实现多值存储单元的 CMOS 实现”IEICE 电子、通信和计算机科学基础汇刊。