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A Study on Circuit-Specialization based on Reconfigurable Logic Devices

基于可重构逻辑器件的电路专业化研究

基本信息

批准号：
16500029
负责人：
ICHIKAWA Shuichi
金额：
$ 2.3万
依托单位：
Toyohashi University of Technology
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (C)
财政年份：
2004
资助国家：
日本
起止时间：
2004 至 2006
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/en/grant/KAKENHI-PROJECT-16500029/
关键词：
FPGA Reconfigurable logic circuit Partial evaluation Custom computing circuit High-performance Reduction of logic scale

项目摘要

Generally, the logic scale of a logic circuit is reduced if some of its inputs are fixed to constant values. The derived circuit becomes smaller and faster than the original, while it is dependent on the input instances and thus not reusable. This kind of technique is called "specialization" or "partial evaluation", which has originally been studied for software. Circuit-specialization is best suited to reconfigurable logic devices (e.g., FPGA), and its applications are not fully explored yet. The purpose of this study is to examine the applications and advantages of circuit-specialization based on reconfigurable logic devices.The results of this study include the following items.1. The design and evaluation of data-dependent hardware for Subgraph Isomorphism problem (IEICE Trans. ED, v.E87-D, pp.2038-2047).2. Custom computing hardware for the 3x+1 problem (IEEE TENCON2004, v.D, pp.387-390), where circuit specialization is effective to improve performance/area ratio (Ann. Mtg. Rec. IEEJ 2005, v.3, pp.87-88).3. Design and evaluation of data-dependent hardware for AES encryption algorithm (IEICE Trans. ED, v.E89-D, pp.2301-2305).4. A method to convert a PLC instruction sequence into hardware description to generate a small and fast control circuit (IEEE ISIE2006, pp. 2930-2935).5. Design and evaluation of hardware Pseudo-Random Number Generator MT19937 (IEICE Trans. ED, v.E88-D, pp. 2876-2879).6. Redundancy in instruction sequences of computer programs (IEICE Trans. EA, v.E89-A, pp.219-221).

通常，如果将逻辑电路的某些输入固定为恒定值，则逻辑电路的逻辑尺度会减小。衍生电路比原始电路变得更小、更快，但它依赖于输入实例，因此不能重复使用。这种技术被称为“专门化”或“部分评估”，最初是针对软件进行研究的。电路专门化最适合于可重构逻辑器件（如FPGA），其应用尚未得到充分探索。本研究的目的是探讨基于可重构逻辑器件的电路专门化的应用与优势。本研究的结果包括以下几个项目。子图同构问题中数据相关硬件的设计与评价。2.中国科学院学报（英文版）。针对3x+1问题的定制计算硬件（IEEE TENCON2004, v.D, pp.387-390），其中电路专业化可以有效提高性能/面积比(Ann。[j] .环境工程学报，2005,vol .3, pp.87-88。AES加密算法中数据相关硬件的设计与评价。3 .中国科学院学报（自然科学版）。4 .将PLC指令序列转换为硬件描述以生成小而快速的控制电路的方法（IEEE ISIE2006, pp. 2930-2935）。硬件伪随机数发生器MT19937 （IEICE Trans）的设计与评价。ED, v.E88-D, pp. 2876-2879)。计算机程序指令序列中的冗余。EA, v.E89-A，第219-221页)。