课题基金 / 基金详情

A Hardware Evaluation System for an Interconnection Network Using Reconfigurable Devices

A Hardware Evaluation System for an Interconnection Network Using Reconfigurable Devices
使用可重构器件的互连网络的硬件评估系统
批准号:
17500051
负责人:
KOHATA Masaki
金额:
$2.18万
依托单位国家:
日本
项目类别:
Grant-in-Aid for Scientific Research (C)
财政年份:
2005
资助国家:
日本
项目状态:
已结题
起止时间:
2005 至 2006

项目摘要

项目成果

相似基金

相关文献

中文摘要
翻译
本研究利用现场可编程门阵列(FPGA)设计并开发了PC集群网卡,并利用该网卡实现了PC集群系统。该网卡为32位PCI总线卡,由1个FPGA、2个ram和4个连接器组成。PCI接口、4个通信接口和1个5口交换机在一个FPGA中实现,通过重新配置FPGA可以改变网络配置。通信速率记录在两个RAM中的一个中,而事件的时间(例如通信开始/结束)记录在另一个RAM中。我们开发了软件,包括网卡的设备驱动程序、通信库和可视化工具。设备驱动程序作为Linux操作系统的内核模块实现。通信库提供了基本的通信功能,如初始化、finalize、发送、接收、广播和屏障同步。此外,还开发了一个重新配置工具,该工具可以从管理PC上重新配置集群中每个PC上的FPGA。我们利用该卡构建了一个环形网络连接的PC机集群系统。为了对系统进行评估,通过重新配置FPGA改变通信缓冲区的深度,对通信性能进行了测量和比较。在执行雅可比法时,利用卡的通信日志功能测量和可视化通信速率和时间。总之,测试确定了系统的基本功能。目前,我们正在将该系统扩展为二维晶格型网络。
英文摘要
In this research, we designed and developed a network card for PC clusters using field programmable gate arrays (FPGA), and realized a PC cluster system with this card. This network card is a 32-bit PCI bus card and consists of one FPGA, two RAMs, and four connectors. The PCI interface, four communication ports, and a five-port switch are implemented in one FPGA, and the network configuration can be changed by reconfiguring the FPGA. The communication rate is recorded in one of the two RAMs, and the timing of events, such as communication start/end, are recorded in another RAM.We developed software, including a device driver for the network card, communication library, and visualization tools. The device driver is implemented as a kernel module for the Linux OS. The communication library provides basic communication functions, such as initialize, finalize, send, receive, broadcast, and barrier synchronization. In addition, a reconfiguration tool was developed, which reconfigures the FPGA in each PC of the cluster from a management PC.We used the card to construct a PC cluster system connected by a ring network. For system evaluation, measurement and comparison of communication performance were performed while changing the depth of the communication buffer by reconfiguring the FPGA. The communication rate and timing were measured and visualized at the execution of Jacobi method, using the card's communication log function.In conclusion, the test confirmed the basic system functions. We are currently expanding the system to a two-dimensional lattice-type network.
期刊论文(3)
专著(0)
科研奖励(0)
会议论文
FPGAによる並列計算機用ネットワークの実績評価システム
基于FPGA的并行计算机网络性能评估系统
DOI: --
发表时间: 2006
期刊: 電子情報通信学会技術研究報告 Vol.106、No.199
影响因子: --
作者: [Akira Uejima, 上嶋明]
通讯作者: 上嶋明
FPGAによる並列計算機用ネットワークの実機評価システム
使用FPGA的并行计算机网络实际评估系统
DOI: --
发表时间: 2006
期刊: 電子情報通信学会技術研究報告 Vol.1O6、No.199
影响因子: --
作者: [Satoshi, Nishizaka, 上嶋明]
通讯作者: 上嶋明
DOI: --
发表时间: 2006
期刊: IEICE Technical Report Vol.106, No.199
影响因子: --
作者: [Akira Uejima]
通讯作者: Akira Uejima
海外基金