Study for a radiation-hardened CMOS circuitdirectly fabricated on a detector-grade silicon wafer with an application of a rapid nitridation process

为了应用于高亮度电子-正电子对撞机实验，我们研究了将条形和/或象素探测器与读出电路集成的可能性。由于电路受到电离粒子和伽马射线的照射，晶体管的特性很容易退化。为了克服辐射损伤的本质，提出的一种方法是对CMOSFET的栅氧化层应用快速热氮化工艺。我们实际上获得了阈值漂移和/或噪声降低方面的改善迹象，但仍有进一步调整工艺条件的空间。提出了用0.8微米的工艺代替目前采用的1.2微米的工艺，在辐射剂量增加时的噪声退化系数和初始噪声斜率方面有了显著的改善。

In order to apply for a high luminosity electron-positron collider experiment we have investigated a possibility of integrating strip and/or pixelde-tectors with a readout circuits. Since the circuits are irradiated by ionizing particles and gamma rays, the characteristics of transistors are easy to be degraded. In order to overcome the nature of a radiation damage, one way proposed was to apply a rapid thermal nitridation process for a gate oxide of a CMOS FET. We actually obtained an indication of an improvement in terms of a threshold shift and/or degradation in noise, there still remained a room for a further adjustment of process conditions. An alternative way was proposed to apply for a 0.8-micron CMOS process in place of the so-far employed 1.2-micron CMOS process, which revealed a significant improvement in terms of a noise degradation coefficient for an increment of a radiation dose as well as an initial noise slope.