Study for Data Acquisition System and Computer Simulation for Super High Energy Hadron Collider (SSC)

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This research is to prepare the study of elementary particle physics such as search for Higgs particles at super high energies using Superconducting Super Collider (SSC). An international experimental team SDC was formed in 1989. Japanese physicists intend to participate SDC in large scale. The project extends over 10 years with the sequence of detector R&D* detector design* construction* physics data taking* data analysis. We just passed the stage of detector design. In order to make the physics experiment feasible, a high technology must be employed in readout electronics, data acquisition, computers including computer simulation. This research aims to promote the R&D and design efforts in the data-acquisition/computer related subjects in conjunction with the support from the Japan-US cooperation in high-energy physics. The achievements under the support of the present research are :(1) Overall design of SDC detector,(2) Development of VLSI for specific detectors, such as silicon and straw trackers, Especially TMC (time memory cell), a new circuit idea of time digitization using CMOS memory technology, was developed and tested by Japanese group.(3) Conceptual design of the event builder with high speed switching devices,(4) Creation of common simulation program for collider events and detector elements and(5) Conceptual design of the off-line computing system for experiment at SSC.