Research on iterative decoding of product code composed of majority logic decodable codes.

提出了一种利用重要抽样法求产品代码权重分布的方法。对代码的性能进行了预测，并通过仿真验证了代码的有效性。提出了三种基于最小可靠性值的简单译码算法。结果表明，当码率小于45/63时，该算法在1 dB范围内性能较差，译码速度较高。利用FPGA设计了基于该算法的硬件解码器。讨论了硬件尺寸和解码速度，指出了需要改进的地方。针对突发脉冲噪声信道，提出了包含噪声状态估计器的分组码和卷积码迭代译码算法。提出了一种卷积码的性能评价方法。针对脉冲噪声信道，提出了产品码的软判决反馈均衡器。对于卷积码，提出了一种基于码与信道复合网格的均衡译码算法。采用软输出viterbi算法，在DSP上设计了一种turbo栅格编码调制的迭代解码器。由于SOVA只需要很少的乘法运算，因此在解码器中没有充分发挥DSP的能力。提出了一种串行串联编码调制，并进行了比较研究。通过增加交错大小，系统的误码率可以迅速降低。

A method to get weight distribution of a product code by using importance sampling is proposed. Performance of the code is predicted and the validity of it is shown by simulation.Three types of simple decoding algorithm based on minimum reliability value is proposed. By comparing the results with those with the chase algorithm, performance is shown inferior within 1 dB and decoding speed is shown higher for a code with rate less than 45/63.A hardware decoder based on the proposed algorithm is design by using FPGA. Scale of the hardware and decoding speed is discussed and necessary improvement is shown.For a bursty impulsive noise channel, iterative decoding algorithm including noise state estimator is proposed for a block code and for a convolutional code. A performance evaluation method is proposed for a convolutional code.For an impulsive noise channel, soft-decision feedback equalizer is proposed for a product code. For a convolutional code, an equlaization and decoding algorithm is derived based on a composite trellis of the code and the channel.A iterative decoder for turbo trellis-coded modulation is designed with soft-output viterbi algorithm (SOVA) on a DSP. Since SOVA needs few multiplications, the ability of DSP is not fully used in the decoder.An serially concatenated coded modulation is proposed and investigated for a comparison. Bit error rate of the proposed system is shown to decrease rapidly by increasing an interleave size.