Research on iterative decoding of product code composed of majority logic decodable codes.

提出了一种利用重要性采样获取产品代码权重分布的方法。对代码的性能进行了预测，并通过仿真验证了代码的有效性。提出了三类基于最小可靠值的简单译码算法。通过与Chase算法的结果比较，对于码率小于45/63的代码，性能表现较差在1dB以内，并且解码速度较高。利用FPGA设计了基于该算法的硬件解码器。讨论了硬件规模和解码速度，并提出了必要的改进。针对突发脉冲噪声信道，提出了针对分组码和卷积码的包含噪声状态估计器的迭代解码算法。提出了一种卷积码的性能评估方法。针对脉冲噪声信道，提出了乘积码的软判决反馈均衡器。针对卷积码，基于码和信道的复合网格推导了均衡译码算法。在DSP上采用软输出维特比算法(SOVA)设计了Turbo网格编码调制的迭代译码器。由于SOVA需要很少的乘法，DSP的能力在解码器中没有得到充分利用。为了进行比较，提出并研究了一种串行级联编码调制。所提出的系统的误码率通过增加交织大小而迅速降低。

A method to get weight distribution of a product code by using importance sampling is proposed. Performance of the code is predicted and the validity of it is shown by simulation.Three types of simple decoding algorithm based on minimum reliability value is proposed. By comparing the results with those with the chase algorithm, performance is shown inferior within 1 dB and decoding speed is shown higher for a code with rate less than 45/63.A hardware decoder based on the proposed algorithm is design by using FPGA. Scale of the hardware and decoding speed is discussed and necessary improvement is shown.For a bursty impulsive noise channel, iterative decoding algorithm including noise state estimator is proposed for a block code and for a convolutional code. A performance evaluation method is proposed for a convolutional code.For an impulsive noise channel, soft-decision feedback equalizer is proposed for a product code. For a convolutional code, an equlaization and decoding algorithm is derived based on a composite trellis of the code and the channel.A iterative decoder for turbo trellis-coded modulation is designed with soft-output viterbi algorithm (SOVA) on a DSP. Since SOVA needs few multiplications, the ability of DSP is not fully used in the decoder.An serially concatenated coded modulation is proposed and investigated for a comparison. Bit error rate of the proposed system is shown to decrease rapidly by increasing an interleave size.