Development of New Digital Signal Processing Circuit for Neural and Fuzzy Systems

神经和模糊系统新型数字信号处理电路的开发

• 批准号: 10650349
• 负责人: TABATA Toru
• 金额: $ 2.24万
• 依托单位: Kumamoto National College of Technology
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for Scientific Research (C)
• 财政年份: 1998
• 资助国家: 日本
• 起止时间: 1998 至 1999
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-10650349/
• 关键词: digital signal processing; parallel arithmetic operation; redundantly-expressed number; binary-coded number; fuzzy processing operation; CMOS-based circuit; decoder; SPICE simulation; 信号処理; 2進化冗長多進PD数; レイアウトパターン設計; 冗長表現多進数; 高速演算; 複号処理; CMOS構

In the field of the digital computer arithmetic, various VLSI technologies for realtime processing of large massive binary data at a very high speed have increasingly come into much efficient meaning out of necessity. We have realized new parallel-processing arithmetic and logical operation circuits using redundantly-represented high-radix positive digit numbers, which can be effective to eliminate the chain transferred delay in the carry process of operation with binary numbers having very large digit-lengths because of its fast processing. By utilizing these basic computation technique for avoiding errors arising from the analog calculation in the conventional analog neural an fuzzy hardware systems, we tried to realize high-speed and high-precision digital signal processing circuits.In 1998, we proposed a new high-speed addition and subtraction algorithm for minimum redundantly-represented high-radix positive digit (PD) numbers which are easy to be transformed into non-redundant bin … More ary numbers, and we realized a new current-mode CMOS-based 5-valued 4-radix PD number addition and subtraction circuit. Furthermore, we realized the fuzzy basic logical operation circuits for logical products, logical sum, bounded sum, bounded difference and bounded product, and max/min discrimination between two redundantly-represented 5-valued 4-radix positive digit numbers which express the fuzzy grades of membership functions.In 1999, in the fourth chapter, in order to construct the complex system with other binary processing systems, we proposed new binary-coded redundant PD number addition, subtraction method and multiplication methods where each digit value can be expressed a set of plural non-redundant bit values. I construct a new voltage-mode CMOS-based adder and subtracter based on logical combinational switch circuit, which is composed of NOT circuits and NAND circuits. Moreover, I realized a new decoder for converting redundant 4-radix PD numbers into pure binary number by using transforming algorithm which is worked as a carry look ahead addition processing.We tested the new adder by using general circuit simulation software, SPICE. We have used the SPICE model parameters of the enhancement type PMOS and NMOS based on the 0.5 μm MOSIS CMOS technology. By the measured results, the maximum propagation delay time of addition are obtained about 3 [ns]. Less

在数字计算机运算领域中，用于以非常高的速度实时处理大量二进制数据的各种VLSI技术已经越来越具有必要的有效意义。我们用冗余表示的高基数正数实现了新的并行处理算术和逻辑运算电路，由于其处理速度快，可以有效地消除具有很大位长的二进制数进位运算过程中的链式转移延迟。利用这些基本的计算技术来避免传统模拟神经和模糊硬件系统中模拟计算所产生的误差，我们试图实现高速和高精度的数字信号处理电路。提出了一种新的最小冗余表示高基数正数（PD）数的快速加减法算法 ...更多信息 提出了一种基于CMOS的电流模式5值4基PD数加减电路。在此基础上，实现了逻辑积、逻辑和、有界和、有界差、有界积的模糊基本逻辑运算电路，以及表示隶属函数模糊等级的两个冗余表示的5值4基正数的最大/最小判别。我们提出了新的二进制编码冗余PD数加法、减法和乘法，其中每个数字值可以表示为多个非冗余比特值的集合。基于逻辑组合开关电路，构造了一种新的电压模式CMOS加法器和减法器，该电路由非电路和与非电路组成。此外，利用超前进位加法处理的变换算法，实现了一种将冗余4基PD数转换为纯二进制数的新的译码器，并利用通用电路仿真软件SPICE对新的加法器进行了测试。我们使用了基于0.5 μm MOSIS CMOS工艺的增强型PMOS和NMOS的SPICE模型参数。测量结果表明，最大加光延迟时间约为3 [ns]。少

项目成果

Toru Tabata, Ueno Fumio, Kei Eguchi and Takahiro Inoue: "CMOS-Based Voltage-Mode Parallel Processing Adder and Subtracter Using Binary Coded 4-Valued 2-Radix positive-Digit Numbers"Proc. Of the 1999 International Symposium on Nonlinear Theory and its Appl

Toru Tabata、Ueno Fumio、Kei Eguchi 和 Takahiro Inoue：“使用二进制编码 4 值 2 基正数的基于 CMOS 的电压模式并行处理加法器和减法器”Proc。

田畑 亨、松本佳子、上野文男: "冗長4進PD数の非冗長2進数への復号回路の構成" 平成10年度電気関係学会九州支部連合大会講演論文集. 110. 9 (1998)

Toru Tabata、Yoshiko Matsumoto、Fumio Ueno：“冗余四进制 PD 数到非冗余二进制数的解码电路的配置”1998 年日本电气工程师九州分会会议记录 110. 9 (1998)。

Toru Tabata, Ueno Fumio and Takahiro Inoue: "Current-Mode Fuzzy Operation circuit Using Positive, Minimum Redundantly-Represented High-radix Number"Proc. Of the 5th International Conference on Soft Computing. 1. 97-100 (1998)

Toru Tabata、Ueno Fumio 和 Takahiro Inoue：“使用正、最小冗余表示高基数的电流模式模糊运算电路”Proc。

Toru Tabata,Ueno Fumio and Takahiro Inoue: "Current-Mode CMOS-Based High-Radix Multiplier Using Minimum-Redundantly Represented Positive-Digit Number" Proc.of the 1998 International Technical Conference on Circuits/Systems,Computers and Communications. Vo

Toru Tabata、Ueno Fumio 和 Takahiro Inoue：“使用最小冗余表示正数的基于电流模式 CMOS 的高基乘法器”1998 年国际电路/系统、计算机和通信技术会议的会议记录。

Toru Tabata, Ueno Fumio, Kei Eguchi and Takahiro Inoue: "CMOS-Based Voltage-Mode Parallel Processing Adder and Substracter Using Binary Coded 4-Valued 2-Radix Positive-Digit Numbers"Proc. Of the 1999 International Symposium on Nonlinear Theory and its App

Toru Tabata、Ueno Fumio、Kei Eguchi 和 Takahiro Inoue：“使用二进制编码 4 值 2 基正数字的基于 CMOS 的电压模式并行处理加法器和减法器”Proc。