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DSP Code Optimization Techniques with Consideration in both Computational Resources and Memory Access

兼顾计算资源和内存访问的 DSP 代码优化技术

基本信息

批准号：
13650398
负责人：
SUGINO Nobuhiko
金额：
$ 0.96万
依托单位：
Tokyo Institute of Technology
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (C)
财政年份：
2001
资助国家：
日本
起止时间：
2001 至 2002
项目状态：
已结题

项目摘要

An indirect addressing digital signal processors (hereafter DSP) with auto-modification is assumed, a new code optimization technique is proposed, where memory allocation phase is intensively coupled with a computational ordering phase.In general, software development for DSP is highly cost consuming, so that powerful programming tools such as high-level language compiler is strongly desired. High performance in generated program codes is usually achieved by effective use of arithmetic units and registers. In most of DSPs, however, memory addressing modes are simplified and efficient memory access becomes another key to achieve high code performance.In this research project, a DSP with indirect addressing with auto-modification is assumed, and its compiler has such structure that computational order is rearranged in intermediate code of sub-instruction level according to the derived arithmetic register assignment and memory allocation. The compiler first counts usage of each variable in the data flow graph (hereafter DFG) of a given program, and selects program variables to be spilled. For the derived DFG, the number of overhead codes is evaluated by code generation followed by memory allocation. Then for the commutative arithmetic operations with memory access, the number of overhead codes is evaluated for all the alternative computational orders, and finally, the code with least overhead code is taken as the result.The proposed code optimization technique is applied to the existing compiler for mPD77230, which has similar memory addressing. Codes generated by the compiler for several examples includes less overhead codes associated with memory access than those derived by conventional compilers, and hence shows the effectiveness of the proposed code optimization technique.

以具有自修改功能的间接寻址数字信号处理器为例，提出了一种新的编码优化技术，该技术将内存分配阶段与计算排序阶段紧密耦合。一般来说，DSP软件开发成本较高，因此迫切需要高级语言编译器等功能强大的编程工具。生成的程序代码的高性能通常是通过有效地使用算术单元和寄存器来实现的。然而，在大多数dsp中，内存寻址模式被简化，高效的内存访问成为实现高代码性能的另一个关键。本研究假设了一种具有自修改间接寻址功能的DSP，其编译器的结构是根据派生的算术寄存器分配和内存分配，在子指令级的中间码中重新排列计算顺序。编译器首先计算给定程序的数据流图（以下简称DFG）中每个变量的使用情况，然后选择要溢出的程序变量。对于派生的DFG，开销代码的数量是通过代码生成和内存分配来计算的。然后，对于具有内存访问的交换算术运算，计算所有可选计算阶数的开销代码数，最后取开销代码最少的代码作为结果。将所提出的代码优化技术应用于具有类似内存寻址的mPD77230现有编译器。在几个示例中，由编译器生成的代码比传统编译器派生的代码包含更少的与内存访问相关的开销代码，因此显示了所提出的代码优化技术的有效性。