Fundamental study on neural chips that processes high-frequency carrier signals adaptively and nonlinearly

自适应非线性处理高频载波信号的神经芯片基础研究

• 批准号: 13835002
• 负责人: HIROSE Akira
• 金额: $ 2.69万
• 依托单位: The University of Tokyo
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for Scientific Research (C)
• 财政年份: 2001
• 资助国家: 日本
• 起止时间: 2001 至 2002
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-13835002/
• 关键词: recurrent neural network; delay-tune equality; signal-voltage symmetry; analog circuit; associative memory; recall characteristics; ニューロ・チップ; コヒーレント型ニューラツネットワーク; P-SOM; 自己組織化; 無線通信; 高周波信号処理; 適応復調; 雑音

Neural networks have to be implemented as an analog hardware (non-pulse type) when used for high-frequency applications (ultra high speed signal processing) or as a massively parellel interface (ultra highly parallel processing). Nevertheless, the analog neural networks have not been investigated widely because oft the unstable behavior affected by noise (including insufficient accuracy of weights and large drift). The characteristics and origins of timing instability, distortion and noise spectrum in high frequency regions has still been unclear. We aim at realizing an effectively useful analog hardware by elucidating the origin of such weakness. We conducted measurement of characteristics of two kinds of associative memories (recurrent networks) ; i. e., a discrete component network and a VDEC custom chip network. The measurement results showed that the recalling process is affected to a great extent by the symmetry of the neuron-unit circuit and the synaptic resistors. Therefore, we have designed two new circuit elements (1)highty signal-voltage-symmetric synaptic resistors and (2)highly delay-time-equal neuron. We have fabricated a new network chip incorporating them through the VDEC and measured the characteristics. We have demonstrated that our chip has an outstanding recalling performance and the symmetry and the delay-tune equality has a critical influence on such recurrent decision circuit. The new circuit elements are applicable to recurrent decision chips in general including future ultra-fast turbo decoders.

当用于高频应用（超高速信号处理）或作为大规模并行接口（超高并行处理）时，神经网络必须作为模拟硬件（非脉冲类型）来实现。然而，由于模拟神经网络受噪声影响的不稳定行为（包括权值精度不足和漂移大），尚未得到广泛的研究。高频区时序不稳定性、畸变和噪声频谱的特征和来源尚不清楚。我们的目标是通过阐明这种弱点的来源来实现一个有效的有用的模拟硬件。我们测量了两种联想记忆（循环网络）的特征；即，一个分立元件网络和一个VDEC定制芯片网络。实验结果表明，神经元单元电路和突触电阻的对称性在很大程度上影响记忆过程。因此，我们设计了两种新的电路元件(1)高度信号电压对称的突触电阻和(2)高度延迟时间相等的神经元。我们通过VDEC制作了一个新的网络芯片，并测量了它们的特性。我们已经证明了我们的芯片具有出色的召回性能，对称性和延迟调谐等式对这种循环决策电路有重要影响。新的电路元件一般适用于循环决策芯片，包括未来的超高速涡轮解码器。

项目成果

A.B.Suksmono, A.Hirose: "InSAR image restoration by using stochastic complex-valued neural network"Int'l Conf. on Knowledge-based Engineering Systems (KES) 2002. Proc.. 643-647 (2002)

A.B.Suksmono、A.Hirose：“使用随机复值神经网络进行 InSAR 图像恢复”国际会议。

A.B.Suksmono, A.Hirose: "A study on interferometric SAR image restoration using complex-valued neural networks and its application to phase unwrapping problem"CEOS SAR Workshop 2001. Proc.. 22 (2001)

A.B.Suksmono、A.Hirose：“使用复值神经网络进行干涉 SAR 图像恢复及其在相位展开问题中的应用的研究”CEOS SAR Workshop 2001. Proc.. 22 (2001)

A.B. Suksmono, A. Hirose: "Adaptive processing of interferometric radar images in "Complex-valued Neural Networks Theories and Applications, ""World Scientific (in press). (2002)

A.B.

A.Hirose, S.Murakkami: "Spatiotemporal eqoations expressing microsoopic two-dimensional membrane potential dynamics"Neurocomputing. (in press).

A.Hirose、S.Murakkami：“表达微声二维膜势动力学的时空方程”神经计算。

A.Hirose, C.Tabata, D.Ishimaru: "Coherent neural network architecture realizing a self-organizing activeness mechanism"Proc. of Int'l Conf. on Knowledge-based Engineering Systems (KES)2001. 576-580 (2001)

A.Hirose、C.Tabata、D.Ishimaru：“实现自组织主动机制的相干神经网络架构”Proc。