Fundamental study on neural chips that processes high-frequency carrier signals adaptively and nonlinearly

点击翻译按钮获取中文摘要

Neural networks have to be implemented as an analog hardware (non-pulse type) when used for high-frequency applications (ultra high speed signal processing) or as a massively parellel interface (ultra highly parallel processing). Nevertheless, the analog neural networks have not been investigated widely because oft the unstable behavior affected by noise (including insufficient accuracy of weights and large drift). The characteristics and origins of timing instability, distortion and noise spectrum in high frequency regions has still been unclear. We aim at realizing an effectively useful analog hardware by elucidating the origin of such weakness. We conducted measurement of characteristics of two kinds of associative memories (recurrent networks) ; i. e., a discrete component network and a VDEC custom chip network. The measurement results showed that the recalling process is affected to a great extent by the symmetry of the neuron-unit circuit and the synaptic resistors. Therefore, we have designed two new circuit elements (1)highty signal-voltage-symmetric synaptic resistors and (2)highly delay-time-equal neuron. We have fabricated a new network chip incorporating them through the VDEC and measured the characteristics. We have demonstrated that our chip has an outstanding recalling performance and the symmetry and the delay-tune equality has a critical influence on such recurrent decision circuit. The new circuit elements are applicable to recurrent decision chips in general including future ultra-fast turbo decoders.