Research on high speed packet management with Reconfigurable Hardware

伴随着网络的加速，开发出具有与网络速度相对应的处理效率的网络设备被认为是困难的。在本研究中，我们打算利用可重写的半导体器件，如现场可编程门阵列来开发能够提高处理速度的网络设备。作为第一个课题，本文研究了网络入侵检测系统的研究与开发，特别是探索了利用可重写器件实现系统的高效执行方案。该系统首先由入侵检测模式形成有限状态机，然后自动转换为硬件描述语言。本课题的研究主题是针对硬件数量的减少，开发基于现场可编程门阵列器件的高效执行处理方案。最后，利用基于非确定有限自动机(NFA)的入侵检测模式匹配电路，实现了超过10Gbps的入侵检测实验系统。在该系统上还实现了对FPGA电路规模的缩小。此外，为了进一步减少FPGA电路的硬件数量，在电路设计中采用了数据压缩技术进行了更多的研究。作为第二个课题，我们提出了在服务器-客户端加密通信中使用FPGA对数据进行加密的可重构系统模型。在这样的系统中，提高FPGA的可用性可以提高系统的性能。因此，发展预测方法对有效减少无用的FPGA重构具有重要意义。为了提高加密的效率，我们提出了一种基于目前收到的请求历史来预测近期请求中使用的加密算法的方法。我们使用广义n元语法模型来进行预测，并验证了它的特性。

Attendant upon the acceleration of network, it is said to be difficult to develop network equipment which has the processing efficiency corresponding the speed of the network. In this research, we are going to develop network equipments which can accelerate the processing speed by using the rewritable semiconductor devices, such as FPGA.As the first topic, research and development of the network IDS ( Intrusion Detection System) is studied, especially the efficient execution scheme of the system using FPGA devices is pursued. The system firstly forms the finite-state machine from IDS patterns, next it is converted to hardware description language automatically. The research themes for this topic are to develop the efficient execution processing scheme based on the FPGA devices with regarding the reduction of the hardware quantity. Finally, IDS experimental system which exceeds 10Gbps was made, by using the IDS pattern matching circuit based on the nondeterministic finite automaton (NFA). On this system the reduction of the circuit scale of FPGA is also realized. Furthermore, in order to do the further reduction of the hardware quantity of the FPGA circuit, more research is pursued by adopting a data compression technique to the circuit design.As the second topic, we propose the reconfigurable system model which use FPGA to encrypt the data in the server-client encryption communication. In such a system, raising the availability of FPGA improves the performance. Therefore, it is important that the development of the prediction method to reducing useless reconfiguration of FPGA effectively. We propose the method of predicting the encryption algorithm used in the near future requests based on history of requests received so far to improve the efficiency of encryption. We employ the generalized n-gram model for that prediction, and verify its characteristics.