A Study on a multi-processor for multi-resolution processing in mobile applications

未来，由于摄像头模块变得便宜，通过移动终端上的摄像头收集视频信息变得流行起来。然而，通过相机获得的原始数据通常信噪比较低，在实际使用之前需要进行大量处理。本项目的研究目标是利用多分辨率处理技术减少原始数据处理的处理量，建立处理器体系结构，在低功耗的情况下达到最高(每秒Ira运算)的处理能力，并具有可编程能力来实现各种应用。对于原始数据处理，使用多分辨率对色彩增强和前景分离算法进行了评估，以减少处理量。彩色图像增强使用HSI颜色系统中H的单一颜色元素，并使用小波变换将其进一步还原为113。通过对Walsh谱域进行由细到粗的处理，使前景分离变得稳定，处理量仅为原来的10%。这两种算法都采用逐像素处理，其中包含许多条件跳转指令，由于跳转指令后的NOP操作较多，不适合处理器的流水线控制。为此，建立了一种不在每个单元处理器中都采用流水线控制的超并行DSP方法。新采用的分段总线法在分块空间运算中效果很好，并且在全搜索运动补偿方面，分段总线法优于脉动法。为了降低芯片的SIRE，在非流水线控制下将时钟频率设为最高，作为初步的硬件评估，进行了FPGA实现，单片FGA可以容纳80年代中期的96个DSP，相当于50K个门数。1000K的门控系统将达到280GOPS。

In future, video information gathering through a camera on a mobile terminals becomes popular because camera modules become cheap. Howeve4 raw data through cameras are generally low SNR, and, therein, requires a lot of processing before actual use. The research target in this project consists of processing amount reduction for raw data handling by use of multi-resolution processing and the processor architecture establishment, which can wale up to TOPS (Ira Operations Per Second) processing capabffity under low power dissipation, with programmable capability for realizing a variety of applications. For raw data handling, color enhancement and foreground separation algorithms are evaluated for processing amount reduction by using multi-resolution. The color image enhancement uses single color element of H in the HSI color system, and it also employs wavelet transform for further reduction to 113. Foreground separation, using fine-to-coarse processing on Walsh spectrum domain, becomes stable and reduces the processing amount to only 10% of the original one. Both algorithms employs pixel wise processing including many conditional jump instructions, pipeline control of processors are not suitable, because of many NOP operations after JUMP instructions. As a result, a super-parallel DSP approach which does not employ pipeline control in every element processor is established for this purpose. The newly employed segment buses works quite well in block wise spatial operations, and it has been shown that segment bus approach is better than Systolic approach in terms of full search motion compensation. In order to reduce chip : sire, the clock frequency employed is set to the highest one under non-pipeline control As a preliminary hardware evaluation, FPGA implementation has been carried out and a single FPGAcan hold 96 DSPs of mid 1980s, resulting 50K gate count equivalently. A 1000K gate system will reach 280GOPS.