Design Methodology for Dynamic Reconfigurable Component Optimization

研究了无线通信中动态可重构组件的低功耗设计方法。本研究提出了一种低功耗、动态可配置的二级可配置解码器模型。利用该模型，可以根据规范生成多个前向纠错（FEC）解码器。此外，通过对无线通信系统调制解调部分的分析，表明通过调整解调电路的采样率和计算精度可以实现低误码率和低功耗系统。

This research studies a low power design methodology for dynamic reconfigurable components in wireless communication applications. In this research, low power and dynamically configurable 2-stage configurable decoder model is proposed. By using this model, several Forward Error Correction (FEC) decoders can be generated according to the specifications. Furthermore, by analysis of modulation and demodulation part of wireless communication systems, low bit error rate and low power system is shown to be realized by adjusting the sampling rate and computational precision of demodulation circuits.