Design verification method of massively parallel arithmetic unit combined using a functional language and the Grid computing system

点击翻译按钮获取中文摘要

The main outcome of this project is to improve the ability to verify that the parallel system. For instance, A proof checker (mathematical theorem prover) has been implemented on the network environment. The target information of circuit configurations describes using a functional language. The output code from the compiler uses to prove the sequence of proof expressions by proof checker. To achieve parallelism, this research project introduced a representation model by Petri net. The "pipeline" mechanism is used as a computational model to explain. Next, this project developed a meta hardware compiler based on a functional programming language. Finally, several formal verification tools have tested in the term of project.