Formal Verification System by using Hardware Compiler Fusioning of Theorem Prover and Model Checker on the Grid Environment

一个对网格计算环境实现的定理证明器融合输出硬件编译器目标实现的各种代码。建立了一个从上游到下游都具有高度一致性的形式化验证系统，从而大大提高了异步并行电路系统的验证能力。目标电路的组态信息用函数式语言系统描述。作为编译器输出的语言系统，我们可以得到目标实现代码和证明类型，以证明检查器。在异步逻辑门元件的四值逻辑二线模型的基础上，用消息传递并行计算机对目标电路进行了建模。最后，证明检查器可以通过电路连接来验证其证明的正确性。

A theorem prover that implements to the grid computing environment fuses the output hardware compiler target implementation various code. To build a formal verification system which is consistent high to function downstream from the upstream, thereby dramatically improving the ability for verification of asynchronous parallel circuit system. The configuration informations of the target circuit has been described on the functional language system. As compiler output of the language system, we can get the target implementation code and the type of proof to proof checker. The target circuit has been modeled by message passing parallel computer based on the 4-valued logic two-wire model of asynchronous logic gate element. Finally, proof checker can verify its correctness proof by using of the circuit connection.