SET Immune Spaceborne LSI Circuit Designs by Embedding Cascade Voltage Switch Logic Circuits, High-speed Gates, and Neuron MOS structures

通过嵌入级联电压开关逻辑（CVSL）电路、高速门和神经元MOS结构，设计了容单事件星载LSI电路。使用SPICE研究了单事件瞬态（SET）对CVSL电路的影响。静态 CVSL 和时钟 CVSL (C2VSL) 电路已利用双多晶硅双金属 N 阱 CMOS 技术成功制造。芯片测量已证实 CVSL 半加器、C2VSL 半加器和 C2VSL 全加器能够正常工作。 SET 仿真结果证实，CVSL 和 C2VSL 电路对 SET 的耐受性有所提高。将 CVSL 和 C2VSL 电路的 SET 容差与传统 CMOS 电路的 SET 容差进行比较，表明 CVSL 和 C2VSL 电路是 SET 容差星载电路的候选者。 CVSL电路比传统CMOS电路硬200多倍，C2VSL电路硬十倍。

Single event tolerant spaceborne LSI circuits have been designed by embedding cascade voltage switch logic (CVSL) circuits, high-speed gates, and neuron MOS structures.Single event transient (SET) effects on CVSL circuits have been investigated using SPICE. Static CVSL and clocked CVSL (C2VSL) circuits have been successfully fabricated utilizing a double polysilicon double metal N-well CMOS technology. A CVSL half adder, a C2VSL half adder and a C2VSL full adder have confirmed to function correctly by the chip measurements. SET simulation results have confirmed that the CVSL and C2VSL circuits have increased tolerance to SET. SET tolerance for the CVSL and C2VSL circuits is compared to that for the conventional CMOS circuits, showing that the CVSL and C2VSL circuits are candidates for a SET tolerant spaceborne circuit. CVSL circuits are more than 200 times harder and C2VSL circuits are ten times harder than conventional CMOS circuits.