SET Immune Spaceborne LSI Circuit Designs by Embedding Cascade Voltage Switch Logic Circuits, High-speed Gates, and Neuron MOS structures

通过嵌入级联电压开关逻辑电路、高速门和神经元MOS结构来进行SET免疫星载LSI电路设计

• 批准号: 21560375
• 负责人: HATANO Hiroshi
• 金额: $ 3万
• 依托单位: Shizuoka Institute of Science and Technology
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for Scientific Research (C)
• 财政年份: 2009
• 资助国家: 日本
• 起止时间: 2009-04-01 至 2014-03-31
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-21560375/
• 关键词: 電子デバイス・機器; デバイス設計、シミュレーション; 放射線、粒子線、宇宙線; デバイス設計; 放射線、粒子線; 宇宙線; シミュレーション

Single event tolerant spaceborne LSI circuits have been designed by embedding cascade voltage switch logic (CVSL) circuits, high-speed gates, and neuron MOS structures.Single event transient (SET) effects on CVSL circuits have been investigated using SPICE. Static CVSL and clocked CVSL (C2VSL) circuits have been successfully fabricated utilizing a double polysilicon double metal N-well CMOS technology. A CVSL half adder, a C2VSL half adder and a C2VSL full adder have confirmed to function correctly by the chip measurements. SET simulation results have confirmed that the CVSL and C2VSL circuits have increased tolerance to SET. SET tolerance for the CVSL and C2VSL circuits is compared to that for the conventional CMOS circuits, showing that the CVSL and C2VSL circuits are candidates for a SET tolerant spaceborne circuit. CVSL circuits are more than 200 times harder and C2VSL circuits are ten times harder than conventional CMOS circuits.

通过嵌入级联电压开关逻辑（CVSL）电路、高速门和神经元MOS结构，设计了单事件容错星载LSI电路。利用SPICE研究了CVSL电路中的单事件瞬态效应。利用双多晶硅双金属n阱CMOS技术，成功制备了静态CVSL和时钟CVSL （C2VSL）电路。一个CVSL半加法器，一个C2VSL半加法器和一个C2VSL全加法器通过芯片测量证实功能正确。仿真结果证实了CVSL和C2VSL电路对SET的容忍度有所提高。将CVSL和C2VSL电路与传统CMOS电路的SET容限进行了比较，表明CVSL和C2VSL电路是具有SET容限的星载电路的候选电路。CVSL电路的强度是传统CMOS电路的200倍以上，C2VSL电路的强度是传统CMOS电路的10倍。

项目成果

Single event effects on static and clocked cascade voltage switch logic circuits

单事件对静态和时钟级联电压开关逻辑电路的影响

• 发表时间: 2009
• 期刊: IEEE Trans. Nuclear Science
• 作者: 設楽修平;他;H. Hatano
• 通讯作者: H. Hatano

Novel test circuit structures using selectively metal-covered transistors for a laser irradiation upset analysis

使用选择性金属覆盖晶体管进行激光辐照翻转分析的新颖测试电路结构

• 发表时间: 2011
• 作者: Hiroshi Hatano

Single event effect analysis on C^2VSL circuit with gated feedback

带门控反馈的C^2VSL电路的单粒子效应分析

• 发表时间: 2010
• 期刊: Proceedings of the 11th European Conference on Radiation Effects on Components and Systems, Langenfeld
• 作者: 佐藤進;内田勝;河村希典;Y. Kanai;H. Hatano
• 通讯作者: H. Hatano

A simulation-based re-examination of single event transient pulse propagation failures in NOR/NAND devices

基于仿真的 NOR/NAND 器件中单事件瞬态脉冲传播故障的重新检查

• 发表时间: 2013
• 作者: 佐藤進;葉茂;H. Hatano
• 通讯作者: H. Hatano

Single event effects on CVSL and CMOS exclusive-OR (EX-OR) circuits

• DOI: 10.1109/radecs.2009.5994567
• 发表时间: 2009-09
• 期刊: 2009 European Conference on Radiation and Its Effects on Components and Systems
• 作者: H. Hatano