Study on calibration technique of large scale mixed-signal integrated circuits
Study on calibration technique of large scale mixed-signal integrated circuits
批准号:
21760264
负责人:
ISHIKURO Hiroki
金额:
$2.91万
依托单位:
依托单位国家:
日本
项目类别:
Grant-in-Aid for Young Scientists (B)
财政年份:
2009
资助国家:
日本
项目状态:
已结题
起止时间:
2009 至 2010
中文摘要
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英文摘要
A monitoring circuit which can detect frequency and transient response of analog circuit blocks in large scale mixed-signal integrated circuits has been developed. A sampling circuit with both positive and negative bootstrapped clock generator has been proposed. Fabricated test chips successfully demonstrated the wide frequency and dynamic range operation. An area efficient phase interpolator has been proposed and designed for the monitoring of phase characteristics of the analog circuit blocks. The size of the developed monitoring circuit is smaller than 0.1mm-square and can be embedded in the LSI for the monitoring and calibration of analog circuit blocks.
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用于模拟离散时间信号处理的高线性度和宽带采样电路
DOI:
--
发表时间:
2009
期刊:
影响因子:
--
作者:
[佐藤守, 阿部寛之, 黒田忠広, 石黒仁揮]
通讯作者:
石黒仁揮
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主页等
DOI:
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发表时间:
期刊:
影响因子:
--
作者:
[]
通讯作者:
A 90nm CMOS Highly Linear Clock Bootstrapped RF Sampler Operating at Wide Frequency Range of 0.5GHz to 5GHz
90nm CMOS 高线性时钟自举射频采样器,工作频率范围为 0.5GHz 至 5GHz
DOI:
--
发表时间:
2009
期刊:
in Proc.2009 IEEE Radio Frequency Integrated Circuits Symposium
影响因子:
--
作者:
[M.Sato, H.Abe, M.Hamada, H.Majima, T.Kuroda, H.Ishikuro]
通讯作者:
H.Ishikuro
A Power Scalable SAR-ADC in 0.18um-CMOS with 0.5V Nano-Watt Operation
采用 0.18um-CMOS 封装、工作电压为 0.5V 纳瓦的功率可扩展 SAR-ADC
DOI:
--
发表时间:
2011
期刊:
Proc.1st International Symposium on Access Spaces in press.
影响因子:
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作者:
[Ryota Sekimoto, Akira Shikata, Hiroki Ishikuro]
通讯作者:
Hiroki Ishikuro
0.5V動作6-bitスケーラブル位相補間器
0.5V 操作 6 位可扩展相位插值器
DOI:
--
发表时间:
2010
期刊:
影响因子:
--
作者:
[H.Ishikawa, K.Shimanaka, 熊木聡]
通讯作者:
熊木聡