High Performance, Low Power Hetero-CMOS Device using Compound Si Wafer

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We developed new technology for high-performance, low-power hetero-junction CMOS comprising InGaAs NMOS and Ge PMOS on a large-dia. Si wafer. Ge chips and InGaAs chips are precisely (<1um accuracy) and tightly bonded (20MPa) on a smooth surface roughness (Ra 0.5 angstrom) of P-TEOS hydrophilic area on a Si wafer by using self-assembly technology. Shallow p-n junction technologies of ion implantation and annealing condition for hetero-junction CMOS are established. We successfully implemented Ge and InGaAs photodiodes on a Si wafer by using these technologies. This study shows the opportunity to manufacture high-performance, low-power Ge/InGaAs hetero-junction CMOS device on an 8/12 inch Si wafer with low cost.