CMOSデバイスに向けたゲルマニウム基板上高誘電率絶縁膜ゲートスタック技術
CMOS器件用锗衬底高介电常数绝缘膜栅叠层技术
基本信息
- 批准号:12J09309
- 负责人:
- 金额:$ 1.28万
- 依托单位:
- 依托单位国家:日本
- 项目类别:Grant-in-Aid for JSPS Fellows
- 财政年份:2012
- 资助国家:日本
- 起止时间:2012 至 2013
- 项目状态:已结题
- 来源:
- 关键词:
项目摘要
Ge channel is one of the most promising solution for CMOS devices in post-Si age. Mobility enhancement is the most critical issue limiting the application of Ge MOSFETS. Recently, although many progresses have been achieved for high mobility Ge MOSFETs, mobility degradation in high normal field region is still severe which strongly reduces the ON state current in Ge MOSFETs. The mechanism of this phenomenon is not clear yet, in spite of importance. Therefore, in our research the physical origins causing high normal field mobility degradation were systematically investigated. Through the evaluation of Hall mobility in Ge MOSFETs, it is found that large amount of surface states exist inside valence and conduction band of Ge, which results in significant decrease of mobile carrier concentration in the channel and rapid reduction of effective mobility of Ge MOSFETs.Additionally, it is confirmed that the surface states inside conduction band of Ge can be passivated by annealing the Ge nMOSFETs in atomic deuterium ambient. Besides of surface states, it is also confirmed that the surface state roughness scattering dominates the mobility in high normal field for Ge MOSFETs, similar with the situation in Si MOSFETs. With decreasing the post oxidation temperature, the surface roughness at GeOx/Ge interfaces can be sufficiently reduced without losing the superior electrical passivation much. As a result, around 20% and 25% mobility enhancement can be realized for Ge pMOSFETs and nMOSFETs, respectively, in a high normal field region of N_s=10^<13> cm^<-2> by reducing the post oxidation temperature from 300℃ down to room temperature.
GE通道是SI后CMOS设备最有前途的解决方案之一。移动性增强是限制GE MOSFET的应用的最关键问题。最近,尽管对于高迁移率GE MOSFET已取得了许多进展,但高正常场区域的迁移率仍然很严重,这大大降低了GE MOSFET中的状态电流。尽管很重要,但这种现象的机制尚不清楚。因此,在我们的研究中,系统地研究了导致高正常现场迁移率降解的物理起源。通过评估GE MOSFET中的Hall流动性,发现大量的表面状态存在于GE的价和传统带中,这导致通道中移动载流子浓度显着降低,并且GE MOSFET的有效迁移率迅速降低。在此方面,可以通过GEENEALEALENEAL播出GEENEREAT,从而通过GEEDERIUM播出了GEENEREAT的表面状态。除表面状态外,还可以证实表面状态粗糙度散射在GE MOSFET的高正常场中占主导地位,与Si MOSFET的情况相似。随着氧化后温度的降低,GEOX/GE界面处的表面粗糙度可以充分降低而不会导致上等电钝化。结果,在n_s = 10^<13> cm^<-2>的高正常场区域中,可以分别实现大约20%和25%的迁移率提高,分别通过降低氧化后温度从300℃下降到室温,分别为N_S = 10^<13> cm^<-2>。
项目成果
期刊论文数量(0)
专著数量(0)
科研奖励数量(0)
会议论文数量(0)
专利数量(0)
High Mobility Strained-Ge pMOSFETs with 0.7-nm Ultrathin EOT using Plasma Post Oxidation Hf0_2/Al_2O_3/GeO_X Gate Stacks and Strain Modulation
使用等离子体后氧化 Hf0_2/Al_2O_3/GeO_X 栅极堆栈和应变调制的具有 0.7 nm 超薄 EOT 的高迁移率应变 Ge pMOSFET
- DOI:
- 发表时间:2013
- 期刊:
- 影响因子:0
- 作者:R. Zhang;W. Chern;X. Yu;M. Takenaka;J. L. Hoyt;S. Takagi
- 通讯作者:S. Takagi
Examination of physical origins limiting effective mobility of Ge MOSFETs and the improvement by atomic deuterium annealing
- DOI:
- 发表时间:2013-06
- 期刊:
- 影响因子:0
- 作者:Rui Zhang;J.C. Lin;Xiao Yu;M. Takenaka;Shinichi Takagi
- 通讯作者:Rui Zhang;J.C. Lin;Xiao Yu;M. Takenaka;Shinichi Takagi
High mobility Ge pMOSFETs with 0.7 nm ultrathin EOT using Hf02/A1203/Ge0x/Ge gate stacks fabricated by plasma post oxidation
使用通过等离子体后氧化制造的 Hf02/A12O3/Ge0x/Ge 栅极叠层,具有 0.7 nm 超薄 EOT 的高迁移率 Ge pMOSFET
- DOI:
- 发表时间:2012
- 期刊:
- 影响因子:0
- 作者:R. Zhang;P. C. Huang;N. Taoka;M. Takenaka;S. Takagi
- 通讯作者:S. Takagi
Suppression of Surface States inside Conduction Band and Effective Mobility Improvement of Ge nMOSFETs by Atomic Deuterium Annealing
通过原子氘退火抑制导带内的表面态并有效提高 Gen nMOSFET 的迁移率
- DOI:
- 发表时间:2013
- 期刊:
- 影响因子:0
- 作者:R. Zhang;J-C. Lin;X. Yu;M. Takenaka and S. Takagi
- 通讯作者:M. Takenaka and S. Takagi
Evidence of layer-by-layer oxidation of Ge surfaces by plasma oxidation through A1203
通过 A1203 等离子氧化对 Ge 表面进行逐层氧化的证据
- DOI:
- 发表时间:2012
- 期刊:
- 影响因子:0
- 作者:R. Zhang;P. C. Huang;M. Takenaka;S. Takagi
- 通讯作者:S. Takagi
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