低電圧動作シリコン系　Ｂｅｙｏｎｄ　ＣＭＯＳデバイスの研究

基于低压工作硅的Beyond CMOS器件研究

• 批准号: 14J09099
• 负责人: 鄭 承旻
• 金额: $ 1.41万
• 依托单位: The University of Tokyo
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for JSPS Fellows
• 财政年份: 2014
• 资助国家: 日本
• 起止时间: 2014-04-25 至 2016-03-31
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-14J09099/
• 关键词: Vth self-adjustment; Ultra-low Vdd operation; Nanowire MOSFET; SRAM stability; Low power CMOS; DIBL effect; Si nanowire

This study suggests a new operation mechanism, Vth self-adjustment, for sub-0.3 V operation even enhancing stability of SRAM cells. Vth self-adjusting MOSFETs show two kinds of Vth states in dynamic characteristics, while they show improved on/off current ratio and S-factor in static characteristics by time-lag of tunneling phenomenon. The Vth shift in dynamic characteristics can be used for enhancing stability of SRAM cells. Furthermore, improved on/off current ratio and S-factor are suitable for low voltage operation. However, Vth self-adjusting MOSFETs with planar structure show crucial short channel effects due to limitation of vertical scaling. Thus, gate-all-around (GAA) nanowire structure is introduced to Vth self-adjusting MOSFETs for strong immunity to short channel effects. In order to enhance Vth self-adjusting characteristics, the GAA nanowire structure is modified through enlarged body factor difference between dynamic and static characteristics. Hence, Vth shift and S-factor improvement become enhanced. Also, tri-gate nanowire MOSFETs with floating gates are successfully fabricated and they show excellent device performance. Finally, they show Vth self-adjusting characteristics even in ultra-low Vdd and these results are recomposed to 6 transistors (6T) SRAM cells using simulation. The 6T SRAM cells with Vth self-adjustment clearly show stability improvement at Vdd = 0.1 V.

这项研究提出了一种新的操作机制，Vth自调整，亚0.3 V的操作，甚至提高SRAM单元的稳定性。Vth自调整MOSFET在动态特性中表现出两种Vth状态，而在静态特性中，由于隧穿现象的时滞作用，Vth自调整MOSFET的通断电流比和S因子得到改善。动态特性中的Vth偏移可用于增强SRAM单元的稳定性。此外，改进的开/关电流比和S因子适合于低电压操作。然而，具有平面结构的Vth自调整MOSFET由于垂直缩放的限制而显示出关键的短沟道效应。因此，栅极全包围（GAA）纳米线结构被引入到Vth自调节MOSFET中，以增强对短沟道效应的免疫力。为了增强Vth自调节特性，通过增大动态和静态特性之间的体因子差来修改GAA纳米线结构。因此，Vth偏移和S因子改善变得增强。此外，三栅极纳米线MOSFET的浮栅成功地制作，它们显示出优异的器件性能。最后，它们显示了Vth自调整特性，即使在超低漏电流，这些结果是重组到6晶体管（6 T）SRAM单元使用模拟。具有Vth自调整功能的6 T SRAM单元在Vth = 0.1 V时的稳定性明显提高。

项目成果

Analysis of Delay Time in Subthreshold CMOS Circuits Operating at Ultra-Low Supply Voltage

超低电源电压下工作的亚阈值CMOS电路的延迟时间分析

• 发表时间: 2014
• 作者: Seung-Min Jung;Takuya Saraya;and Toshiro Hiramoto
• 通讯作者: and Toshiro Hiramoto

Effect of drain-induced barrier lowering on performance of ultralow-supply-voltage region

漏极感应势垒降低对超低电源电压区域性能的影响

• DOI: 10.7567/jjap.53.124301
• 发表时间: 2014
• 期刊: Japanese Journal of Applied Physics
• 影响因子: 1.5
• 作者: Seung-Min Jung;Tomoko Mizutani;and Toshiro Hiramoto
• 通讯作者: and Toshiro Hiramoto

Tri-gate Floating Gate Nanowire MOSFETs with Vth Self-adjustment for Improvement of SRAM Cells Stability in Sub-0.3 V Operation

具有 Vth 自调节功能的三栅极浮栅纳米线 MOSFET，可提高 SRAM 单元在低于 0.3 V 运行时的稳定性

• 发表时间: 2015
• 作者: Seung-Min Jung;Takuya Saraya;Kiyoshi Takeuchi;Masaharu Kobayashi;and Toshiro Hiramoto
• 通讯作者: and Toshiro Hiramoto

Ultra-low voltage (0.1V) operation of Vth self-adjusting MOSFET and SRAM cell

• DOI: 10.1109/vlsit.2014.6894416
• 发表时间: 2014-06
• 期刊: 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers
• 作者: A. Ueda;Seungmin Jung;T. Mizutani;Ashok Kumar;T. Saraya;T. Hiramoto

Analysis of Delay Time Degradation of Ultra-Low Supply Voltage CMOS Circuit Operating in Subthreshold Region

亚阈值区超低电源电压CMOS电路延迟时间劣化分析

• 发表时间: 2014
• 作者: Seung-Min Jung;Takuya Saraya;Masaharu Kobayashi;and Toshiro Hiramoto
• 通讯作者: and Toshiro Hiramoto