低電圧動作シリコン系　Ｂｅｙｏｎｄ　ＣＭＯＳデバイスの研究

这项研究提出了一种新的操作机制，Vth自调整，亚0.3 V的操作，甚至提高SRAM单元的稳定性。Vth自调整MOSFET在动态特性中表现出两种Vth状态，而在静态特性中，由于隧穿现象的时滞作用，Vth自调整MOSFET的通断电流比和S因子得到改善。动态特性中的Vth偏移可用于增强SRAM单元的稳定性。此外，改进的开/关电流比和S因子适合于低电压操作。然而，具有平面结构的Vth自调整MOSFET由于垂直缩放的限制而显示出关键的短沟道效应。因此，栅极全包围（GAA）纳米线结构被引入到Vth自调节MOSFET中，以增强对短沟道效应的免疫力。为了增强Vth自调节特性，通过增大动态和静态特性之间的体因子差来修改GAA纳米线结构。因此，Vth偏移和S因子改善变得增强。此外，三栅极纳米线MOSFET的浮栅成功地制作，它们显示出优异的器件性能。最后，它们显示了Vth自调整特性，即使在超低漏电流，这些结果是重组到6晶体管（6 T）SRAM单元使用模拟。具有Vth自调整功能的6 T SRAM单元在Vth = 0.1 V时的稳定性明显提高。

This study suggests a new operation mechanism, Vth self-adjustment, for sub-0.3 V operation even enhancing stability of SRAM cells. Vth self-adjusting MOSFETs show two kinds of Vth states in dynamic characteristics, while they show improved on/off current ratio and S-factor in static characteristics by time-lag of tunneling phenomenon. The Vth shift in dynamic characteristics can be used for enhancing stability of SRAM cells. Furthermore, improved on/off current ratio and S-factor are suitable for low voltage operation. However, Vth self-adjusting MOSFETs with planar structure show crucial short channel effects due to limitation of vertical scaling. Thus, gate-all-around (GAA) nanowire structure is introduced to Vth self-adjusting MOSFETs for strong immunity to short channel effects. In order to enhance Vth self-adjusting characteristics, the GAA nanowire structure is modified through enlarged body factor difference between dynamic and static characteristics. Hence, Vth shift and S-factor improvement become enhanced. Also, tri-gate nanowire MOSFETs with floating gates are successfully fabricated and they show excellent device performance. Finally, they show Vth self-adjusting characteristics even in ultra-low Vdd and these results are recomposed to 6 transistors (6T) SRAM cells using simulation. The 6T SRAM cells with Vth self-adjustment clearly show stability improvement at Vdd = 0.1 V.