低電圧動作シリコン系 Beyond CMOSデバイスの研究
低電圧動作シリコン系 Beyond CMOSデバイスの研究
批准号:
14J09099
负责人:
鄭 承旻
金额:
$1.41万
依托单位:
依托单位国家:
日本
项目类别:
Grant-in-Aid for JSPS Fellows
财政年份:
2014
资助国家:
日本
项目状态:
已结题
起止时间:
2014-04-25 至 2016-03-31
中文摘要
这项研究提出了一种新的工作机制,即Vth自调节,可以在0.3V以下工作,甚至可以提高SRAM单元的稳定性。Vth自调整MOSFET在动态特性上表现出两种Vth态,而在静态特性上由于隧穿现象的滞后而表现出改善的通断电流比和S因数。动态特性中的Vth漂移可用于提高SRAM单元的稳定性。此外,改进的通断电流比和S因数适用于低电压运行。然而,由于垂直尺寸的限制,平面结构的Vth自调整MOSFET显示出关键的短沟效应。因此,在Vth自调整MOSFET中引入了栅通绕(GAA)纳米线结构,从而对短沟效应具有很强的免疫力。为了增强Vth的自调节特性,通过扩大动态特性和静态特性的体因子差,对GaA纳米线结构进行了改进。因此,Vth漂移和S因子的改进变得更加重要。此外,还成功地制作了具有浮栅的三栅纳米线MOSFET,并显示出优异的器件性能。最后,即使在超低Vdd的情况下,它们也表现出Vth自调节特性,并通过仿真将这些结果重组为6个晶体管(6T)SRAM单元。具有Vth自调节功能的6T SRAM单元在Vdd=0.1V时表现出明显的稳定性改善。
英文摘要
This study suggests a new operation mechanism, Vth self-adjustment, for sub-0.3 V operation even enhancing stability of SRAM cells. Vth self-adjusting MOSFETs show two kinds of Vth states in dynamic characteristics, while they show improved on/off current ratio and S-factor in static characteristics by time-lag of tunneling phenomenon. The Vth shift in dynamic characteristics can be used for enhancing stability of SRAM cells. Furthermore, improved on/off current ratio and S-factor are suitable for low voltage operation. However, Vth self-adjusting MOSFETs with planar structure show crucial short channel effects due to limitation of vertical scaling. Thus, gate-all-around (GAA) nanowire structure is introduced to Vth self-adjusting MOSFETs for strong immunity to short channel effects. In order to enhance Vth self-adjusting characteristics, the GAA nanowire structure is modified through enlarged body factor difference between dynamic and static characteristics. Hence, Vth shift and S-factor improvement become enhanced. Also, tri-gate nanowire MOSFETs with floating gates are successfully fabricated and they show excellent device performance. Finally, they show Vth self-adjusting characteristics even in ultra-low Vdd and these results are recomposed to 6 transistors (6T) SRAM cells using simulation. The 6T SRAM cells with Vth self-adjustment clearly show stability improvement at Vdd = 0.1 V.
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Analysis of Delay Time in Subthreshold CMOS Circuits Operating at Ultra-Low Supply Voltage
超低电源电压下工作的亚阈值CMOS电路的延迟时间分析
DOI:
--
发表时间:
2014
期刊:
影响因子:
--
作者:
[Seung-Min Jung, Takuya Saraya, and Toshiro Hiramoto]
通讯作者:
and Toshiro Hiramoto
Effect of drain-induced barrier lowering on performance of ultralow-supply-voltage region
漏极感应势垒降低对超低电源电压区域性能的影响
DOI:
10.7567/jjap.53.124301
发表时间:
2014
期刊:
Japanese Journal of Applied Physics
影响因子:
1.5
作者:
[Seung-Min Jung, Tomoko Mizutani, and Toshiro Hiramoto]
通讯作者:
and Toshiro Hiramoto
Tri-gate Floating Gate Nanowire MOSFETs with Vth Self-adjustment for Improvement of SRAM Cells Stability in Sub-0.3 V Operation
具有 Vth 自调节功能的三栅极浮栅纳米线 MOSFET,可提高 SRAM 单元在低于 0.3 V 运行时的稳定性
DOI:
--
发表时间:
2015
期刊:
影响因子:
--
作者:
[Seung-Min Jung, Takuya Saraya, Kiyoshi Takeuchi, Masaharu Kobayashi, and Toshiro Hiramoto]
通讯作者:
and Toshiro Hiramoto
DOI:
10.1109/vlsit.2014.6894416
发表时间:
2014-06
期刊:
2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers
影响因子:
--
作者:
[A. Ueda;Seungmin Jung;T. Mizutani;Ashok Kumar;T. Saraya;T. Hiramoto]
通讯作者:
A. Ueda;Seungmin Jung;T. Mizutani;Ashok Kumar;T. Saraya;T. Hiramoto
Analysis of Delay Time Degradation of Ultra-Low Supply Voltage CMOS Circuit Operating in Subthreshold Region
亚阈值区超低电源电压CMOS电路延迟时间劣化分析
DOI:
--
发表时间:
2014
期刊:
影响因子:
--
作者:
[Seung-Min Jung, Takuya Saraya, Masaharu Kobayashi, and Toshiro Hiramoto]
通讯作者:
and Toshiro Hiramoto