A HW-SW design and execution platform for sustainable edge-computing devices based on HDLRuby

基于 HDLRuby 的可持续边缘计算设备的硬件-软件设计和执行平台

• 批准号: 22K11965
• 负责人: Gauthier Lovic
• 金额: $ 2.5万
• 依托单位: Ariake National College of Technology
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for Scientific Research (C)
• 财政年份: 2022
• 资助国家: 日本
• 起止时间: 2022-04-01 至 2027-03-31
• 项目状态: 未结题
• 来源: https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-22K11965/
• 关键词: HDL; RTL simulation; HW/SW Co-Design; エッジ・コンピューティング; ハードウェ・ソフトウェアシステム; ハードウェア・ソフトウェア・コードサイン; ハードウェア・ソフトウェア記述言語

The research aims to provide a design flow for digital devices based on the HDLRuby hardware description language, focusing on design productivity and seamless hardware/software integration. During the year, the implementation of an efficient register transfer level (RTL) simulator for HDLRuby has been explored leading to the proposal of a hybrid solution whose performance surpasses the popular simulator Icarus Verilog (1). A full evaluation of the efficiency of HDLRuby for describing complex hardware using high-level software paradigms like object-oriented programming and genericity has also been done for several edge-computing applications including convolutional neural networks (2). In the evaluation, the design time, the file sizes, the hardware synthesis time, and the efficiency of the resulting hardware have been considered for comparing the HDLRuby flow with a standard Verilog HDL one. The results showed that for resulting hardware with identical performance, the design time with HDLRuby was faster, a much more scalable. Both works lead to the following publications:(1) Implementation and Comparison of Several Register Transfer Level Simulation Engines for the HDLRuby Language (ICIAE 2023)(2) HDLRuby: A Ruby Extension for Hardware Description and its Translation to Synthesizable Verilog HDL (ACM TECS 2023)

本研究旨在提供一种基于HDLRuby硬件描述语言的数字设备设计流程，重点关注设计生产力和硬件/软件无缝集成。在这一年中，对HDLRuby的高效寄存器传输级别（RTL）模拟器的实现进行了探索，从而提出了一个混合解决方案，其性能超过了流行的模拟器Icarus Verilog(1)。对HDLRuby在使用高级软件范例（如面向对象编程和泛型）描述复杂硬件方面的效率进行了全面评估，该研究也针对包括卷积神经网络在内的几个边缘计算应用进行了评估(2)。在评估中，考虑了HDLRuby流与标准Verilog HDL流的设计时间、文件大小、硬件合成时间和所得硬件的效率。结果表明，对于具有相同性能的最终硬件，使用HDLRuby的设计时间更快，更具可伸缩性。这两项工作导致以下出版物：(1)HDLRuby语言的几个寄存器传输级仿真引擎的实现和比较（ICIAE 2023）(2) HDLRuby：硬件描述的Ruby扩展及其对可合成Verilog HDL的翻译（ACM TECS 2023）

项目成果

HDLRuby: A Ruby Extension for Hardware Description and its Translation to Synthesizable Verilog HDL

• DOI: 10.1145/3581757
• 发表时间: 2023-02
• 期刊: ACM Transactions on Embedded Computing Systems
• 影响因子: 2
• 作者: Gauthier Lovic;Ishikawa Yohei

Implementation and Comparison of Several Register Transfer Level Simulation Engines for the HDLRuby Language

HDLRuby语言几种寄存器传输级仿真引擎的实现与比较

• 发表时间: 2023
• 期刊: Proceedings of The 11th IIAE International Conference on Industrial Application Engineering 2023
• 作者: Lovic Gauthier;Yohei Ishikawa
• 通讯作者: Yohei Ishikawa