A HW-SW design and execution platform for sustainable edge-computing devices based on HDLRuby

该研究旨在提供一个基于HDLRuby硬件描述语言的数字设备设计流程，重点是设计生产力和无缝的硬件/软件集成。在这一年中，我们探索了一个高效的HDL Ruby寄存器传输级（RTL）模拟器的实现，从而提出了一个混合解决方案，其性能超过了流行的模拟器Icarus Verilog（1）。对HDLRuby使用面向对象编程和泛型等高级软件范例描述复杂硬件的效率进行了全面评估，也针对包括卷积神经网络在内的几个边缘计算应用程序进行了评估（2）。在评估中，设计时间，文件大小，硬件合成时间，以及所得到的硬件的效率已被认为是比较的HDLRuby流与标准的Verilog HDL之一。结果表明，对于具有相同性能的硬件，HDLRuby的设计时间更快，可扩展性更强。这两项工作导致以下出版物：（1）HDL Ruby语言的几种寄存器传输级仿真引擎的实现和比较（ICIAE 2023）（2）HDL Ruby：硬件描述的Ruby扩展及其到可合成Verilog HDL的翻译（ACM TECS 2023）

The research aims to provide a design flow for digital devices based on the HDLRuby hardware description language, focusing on design productivity and seamless hardware/software integration. During the year, the implementation of an efficient register transfer level (RTL) simulator for HDLRuby has been explored leading to the proposal of a hybrid solution whose performance surpasses the popular simulator Icarus Verilog (1). A full evaluation of the efficiency of HDLRuby for describing complex hardware using high-level software paradigms like object-oriented programming and genericity has also been done for several edge-computing applications including convolutional neural networks (2). In the evaluation, the design time, the file sizes, the hardware synthesis time, and the efficiency of the resulting hardware have been considered for comparing the HDLRuby flow with a standard Verilog HDL one. The results showed that for resulting hardware with identical performance, the design time with HDLRuby was faster, a much more scalable. Both works lead to the following publications:(1) Implementation and Comparison of Several Register Transfer Level Simulation Engines for the HDLRuby Language (ICIAE 2023)(2) HDLRuby: A Ruby Extension for Hardware Description and its Translation to Synthesizable Verilog HDL (ACM TECS 2023)