低消費電力メニーコアプロセッサのための非同期式アーキテクチャの開拓

开创了低功耗众核处理器的异步架构

• 批准号: 13J06949
• 负责人: 夏 徴帆
• 金额: $ 0.64万
• 依托单位: Tohoku University
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for JSPS Fellows
• 财政年份: 2013
• 资助国家: 日本
• 起止时间: 2013 至 无数据
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-13J06949/
• 关键词: Asynchronous Pipeline; Self-Adaptive Control

Recently, multi-core design of VLSI systems becomes popular. Although current CMOS technology is capable of integrating enough transistors to realize multi-core system, the classic synchronous design method of VLSI systems leads to severe design challenges because of its bad flexibility. Therefore, the industry is giving serious consideration to the adoption of asynchronous design method to make full use of multi-core architecture. For example, Qualcomm announced multi-core Snapdragon S4 with their asynchronous SIM micro-architecture at MWC2012.This research aims at asynchronous technology to develop high-efficiency asynchronous pipeline and asynchronous self-adaptive multi-voltage control scheme for multi-core VLSI systems. These two technologies would greatly improve the performance of throughput and power consumption. There are two achievements :First, an efficient asynchronous domino logic pipeline (APCDP) is developed. APCDP is constructed based on constructed critical data path. Dual-rail domino logic is used to construct a stable critical data path. Single-rail domino logic is applied in non-critieal data paths. A high-speed encoding converter is designed to bridge the connection between dual-rail logic and single-rail logic.Second, an efficient self-adaptive multi-voltage control scheme is proposed for saving power in asynchronous FPGA. An efficient self-adaptive control is designed, which evaluates the non-critical paths on-line and autonomously assigns a low supply voltage to save power. In normal state, non-critical paths work at low voltage. In low speed state, all paths are assigned with low voltage to save more power.

近年来，超大规模集成电路系统的多核设计越来越流行。虽然目前的CMOS工艺能够集成足够的晶体管来实现多核系统，但经典的VLSI系统同步设计方法灵活性差，给设计带来了严峻的挑战。因此，业界正在认真考虑采用异步设计方法，以充分利用多核架构。例如，高通公司在MWC2012上发布了采用异步SIM微架构的多核Snapdragon S4。本研究旨在针对异步技术，开发适用于多核VLSI系统的高效异步流水线和异步自适应多电压控制方案。这两种技术将大大提高吞吐量和功耗的性能。本文的主要成果有两个：第一，提出了一种高效的异步多米诺逻辑流水线（APCDP）。APCDP是在已构造的关键数据通路的基础上构造的，采用双轨多米诺逻辑构造稳定的关键数据通路，采用单轨多米诺逻辑构造非关键数据通路。设计了一种高速编码转换器，实现了双轨逻辑与单轨逻辑之间的连接。其次，提出了一种高效的异步FPGA自适应多电压控制方案。设计了一种有效的自适应控制器，在线评估非关键路径，并自主分配低电源电压以节省功率。在正常状态下，非关键路径在低电压下工作。在低速状态下，所有路径被分配以低电压以节省更多功率。

项目成果

A Low-Power FPGA Based on Self-Adaptive Multi-Voltage Control

基于自适应多电压控制的低功耗FPGA

• 发表时间: 2013
• 期刊: Proc. International SoC Design Conference
• 作者: Zhengfan Xia;Masanori Hariyama;Michitaka Kameyama
• 通讯作者: Michitaka Kameyama