低消費電力メニーコアプロセッサのための非同期式アーキテクチャの開拓

近年来，VLSI系统的多核设计成为一种流行趋势。虽然目前的CMOS工艺能够集成足够多的晶体管来实现多核系统，但经典的VLSI系统同步设计方法由于灵活性差而导致设计面临严峻的挑战。因此，业界正在认真考虑采用异步设计方法，充分利用多核架构。例如，高通在MWC2012上发布了带有异步SIM微架构的多核骁龙S4。本研究针对异步技术，为多核VLSI系统开发高效的异步流水线和异步自适应多电压控制方案。这两种技术将大大提高系统的吞吐量和功耗性能。取得了两项成果：一是开发了高效的异步多米诺逻辑流水线(APCDP)。APCDP是基于构建的关键数据路径构建的。采用双轨多米诺骨牌逻辑构建稳定的关键数据路径。单轨多米诺逻辑应用于非临界数据路径。设计了一种用于连接双轨逻辑和单轨逻辑的高速编码转换器；其次，提出了一种高效的自适应多电压控制方案，用于异步现场可编程门阵列的节能。设计了一种高效的自适应控制，在线评估非关键路径，并自主分配较低的电源电压以节省电能。在正常状态下，非关键路径工作在低电压下。在低速状态下，为所有路径分配低电压，以节省更多功率。

Recently, multi-core design of VLSI systems becomes popular. Although current CMOS technology is capable of integrating enough transistors to realize multi-core system, the classic synchronous design method of VLSI systems leads to severe design challenges because of its bad flexibility. Therefore, the industry is giving serious consideration to the adoption of asynchronous design method to make full use of multi-core architecture. For example, Qualcomm announced multi-core Snapdragon S4 with their asynchronous SIM micro-architecture at MWC2012.This research aims at asynchronous technology to develop high-efficiency asynchronous pipeline and asynchronous self-adaptive multi-voltage control scheme for multi-core VLSI systems. These two technologies would greatly improve the performance of throughput and power consumption. There are two achievements :First, an efficient asynchronous domino logic pipeline (APCDP) is developed. APCDP is constructed based on constructed critical data path. Dual-rail domino logic is used to construct a stable critical data path. Single-rail domino logic is applied in non-critieal data paths. A high-speed encoding converter is designed to bridge the connection between dual-rail logic and single-rail logic.Second, an efficient self-adaptive multi-voltage control scheme is proposed for saving power in asynchronous FPGA. An efficient self-adaptive control is designed, which evaluates the non-critical paths on-line and autonomously assigns a low supply voltage to save power. In normal state, non-critical paths work at low voltage. In low speed state, all paths are assigned with low voltage to save more power.