低消費電力メニーコアプロセッサのための非同期式アーキテクチャの開拓

开创了低功耗众核处理器的异步架构

• 批准号: 13J06949
• 负责人: 夏 徴帆
• 金额: $ 0.64万
• 依托单位: Tohoku University
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for JSPS Fellows
• 财政年份: 2013
• 资助国家: 日本
• 起止时间: 2013 至 无数据
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-13J06949/
• 关键词: Asynchronous Pipeline; Self-Adaptive Control

Recently, multi-core design of VLSI systems becomes popular. Although current CMOS technology is capable of integrating enough transistors to realize multi-core system, the classic synchronous design method of VLSI systems leads to severe design challenges because of its bad flexibility. Therefore, the industry is giving serious consideration to the adoption of asynchronous design method to make full use of multi-core architecture. For example, Qualcomm announced multi-core Snapdragon S4 with their asynchronous SIM micro-architecture at MWC2012.This research aims at asynchronous technology to develop high-efficiency asynchronous pipeline and asynchronous self-adaptive multi-voltage control scheme for multi-core VLSI systems. These two technologies would greatly improve the performance of throughput and power consumption. There are two achievements :First, an efficient asynchronous domino logic pipeline (APCDP) is developed. APCDP is constructed based on constructed critical data path. Dual-rail domino logic is used to construct a stable critical data path. Single-rail domino logic is applied in non-critieal data paths. A high-speed encoding converter is designed to bridge the connection between dual-rail logic and single-rail logic.Second, an efficient self-adaptive multi-voltage control scheme is proposed for saving power in asynchronous FPGA. An efficient self-adaptive control is designed, which evaluates the non-critical paths on-line and autonomously assigns a low supply voltage to save power. In normal state, non-critical paths work at low voltage. In low speed state, all paths are assigned with low voltage to save more power.

近年来，超大规模集成电路系统的多核设计成为流行趋势。虽然目前的CMOS技术能够集成足够多的晶体管来实现多核系统，但超大规模集成电路系统的经典同步设计方法由于灵活性差，给设计带来了严峻的挑战。因此，业界正在认真考虑采用异步设计方法来充分利用多核架构。例如，高通在MWC2012上发布了多核Snapdragon S4及其异步SIM微架构。本课题以异步技术为研究对象，为多核VLSI系统开发高效异步管道和异步自适应多电压控制方案。这两种技术将大大提高吞吐量和功耗的性能。本文取得了两个成果：首先，开发了一种高效的异步domino逻辑管道（APCDP）。APCDP是基于已构建的关键数据路径构建的。双轨domino逻辑用于构建稳定的关键数据路径。单轨domino逻辑应用于非关键数据路径。设计了一种高速编码转换器，以桥接双轨逻辑与单轨逻辑之间的连接。其次，提出了一种高效的多电压自适应控制方案，以节省异步FPGA的功耗。设计了一种有效的自适应控制，在线评估非关键路径并自动分配低电源电压以节省电力。在正常情况下，非关键路径工作在低电压下。在低速状态下，所有路径都被分配低电压，以节省更多的电力。

项目成果

A Low-Power FPGA Based on Self-Adaptive Multi-Voltage Control

基于自适应多电压控制的低功耗FPGA

• 发表时间: 2013
• 期刊: Proc. International SoC Design Conference
• 作者: Zhengfan Xia;Masanori Hariyama;Michitaka Kameyama
• 通讯作者: Michitaka Kameyama