低消費電力デバイス向け化合物半導体と高誘電率絶縁膜及び金属電極の界面設計指針創出

为低功耗器件的化合物半导体、高介电常数绝缘膜和金属电极制定界面设计指南

• 批准号: 13J08817
• 负责人: ハサンザデ ダリューシュ
• 金额: $ 1.32万
• 依托单位: Tokyo Institute of Technology
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for JSPS Fellows
• 财政年份: 2013
• 资助国家: 日本
• 起止时间: 2013 至 2014
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-13J08817/
• 关键词: Atomic layer deposition; La203; InGaAs; MOSFET; Interface state traps; transconductance; 高誘電率絶膜; 界面準位; 熱安定性; 界面層

This research focuses on understanding and engineering the interface at high-k and InGaAs for enabling low power, high performance devices for application in mobile devices. Rare metal earth oxide La203 is chosen as the high-k oxide in this research. The main issues facing high-k/InGaAs interface, is the formation of unstable oxides which lead to formation of several types of defects such as interface traps (Dit) and bulk traps within both the oxide and substrate. However, it was found that extremely low defect interfaces can be fabricated by using La203 due to formation of LaInGaO interfacial layer. This interfacial layer has an amorphous nature and prevents the formation of unstable oxides, thus improving the quality of the interface. Lowest reported Dit on smallest equivalent oxide thickness on InGaAs substrates in the order of lower 10 to the power of 11 was reported by atomic layer deposition(ALD) of La203 on InGaAs conducted in this research. Due to prevalence of finFET design in … More recent devices structures, it is important to evaluate the characteristics of La203 interface on various orientations of InGaAs substrate. Contrary to a planar device structure, the device channel region in a FinFET device is composed of multiple orientations. Therefore, it is important to achieve high quality interface on all substrate orientations in order to benefit from the superior electrostatic gate properties of the finFET designs. In this research, MOSFETs with ALD-deposited La203 oxide on [100], [110] and [111] oriented InGaAs substrates were fabricated. All p-type substrates used in MOSFETs had pre-formed source and drain regions. It was found that a similiar Dit can be achieved on all substrates. The substhreshold swing in all MOSFETs was ~130 mV/dec which imply similar interface characteristics. However, higher drain current and transconductance values were achieved for the substrate with [111] orientation. This effect could be related to lower effective mass of electrons in this surface which is a material property of crystalline surface. These resutls show the potential for using La203 in various InGaAs devices in idustry. Less

本研究的重点是理解和设计高k和InGaAs的接口，以使低功耗，高性能的设备应用于移动设备。本研究选用稀土氧化物La203作为高钾氧化物。高k/InGaAs界面面临的主要问题是形成不稳定的氧化物，导致氧化物和衬底内形成几种类型的缺陷，如界面陷阱（Dit）和大块陷阱。然而，由于La203形成了LaInGaO界面层，因此可以制备极低缺陷的界面。该界面层具有无定形性质，可防止不稳定氧化物的形成，从而提高界面质量。在InGaAs衬底上进行La203的原子层沉积（ALD），在最小的等效氧化物厚度上报道了最低的Dit，约为10的11次方。由于finFET设计在最近器件结构中的流行，因此评估不同取向InGaAs衬底上La203接口的特性非常重要。与平面器件结构相反，FinFET器件中的器件通道区域由多个方向组成。因此，为了从finFET设计的优越静电栅极特性中获益，在所有基板方向上实现高质量的接口是很重要的。在本研究中，在[100]，[110]和[111]取向InGaAs衬底上制备了ald沉积La203氧化物的mosfet。所有用于mosfet的p型衬底都具有预先形成的源极和漏极区。结果表明，在所有的衬底上都可以得到相似的Dit。所有mosfet的亚阈值摆幅均为~130 mV/dec，表明界面特性相似。然而，具有[111]取向的衬底可以获得更高的漏极电流和跨导值。这种效应可能与晶体表面较低的有效电子质量有关，这是晶体表面的材料特性。这些结果显示了在工业中各种InGaAs器件中使用La203的潜力。少

项目成果

Scalable La-silicate Gate Dielectric on InGaAs Substrate with High Thermal Stability and Low Interface State Densit

InGaAs 衬底上的可扩展硅酸铝栅极电介质，具有高热稳定性和低界面态密度

• 发表时间: 2013
• 作者: J. Naganawa;et al.;Daryoush Hassan Zadeh;Daryoush Hassan Zadeh
• 通讯作者: Daryoush Hassan Zadeh

Low Dit high-k/In0.53Ga0.47As gate stack, with CET down to 0.73 nm and thermally stable silicide contact by suppression of interfacial reaction

低 Dit 高 k/In0.53Ga0.47As 栅极堆叠，CET 低至 0.73 nm，通过抑制界面反应实现热稳定硅化物接触

• DOI: 10.1109/iedm.2013.6724544
• 发表时间: 2013
• 期刊: 2013 IEEE International Electron Devices Meeting
• 作者: D. Zadeh;H. Oomine;K. Kakushima;Y. Kataoka;A. Nishiyama;N. Sugii;H. Wakabayashi;K. Tsutsui;K. Natori;H. Iwai
• 通讯作者: H. Iwai