低消費電力デバイス向け化合物半導体と高誘電率絶縁膜及び金属電極の界面設計指針創出
低消費電力デバイス向け化合物半導体と高誘電率絶縁膜及び金属電極の界面設計指針創出
批准号:
13J08817
负责人:
ハサンザデ ダリューシュ
金额:
$1.32万
依托单位国家:
日本
项目类别:
Grant-in-Aid for JSPS Fellows
财政年份:
2013
资助国家:
日本
项目状态:
已结题
起止时间:
2013 至 2014
中文摘要
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英文摘要
This research focuses on understanding and engineering the interface at high-k and InGaAs for enabling low power, high performance devices for application in mobile devices. Rare metal earth oxide La203 is chosen as the high-k oxide in this research. The main issues facing high-k/InGaAs interface, is the formation of unstable oxides which lead to formation of several types of defects such as interface traps (Dit) and bulk traps within both the oxide and substrate. However, it was found that extremely low defect interfaces can be fabricated by using La203 due to formation of LaInGaO interfacial layer. This interfacial layer has an amorphous nature and prevents the formation of unstable oxides, thus improving the quality of the interface. Lowest reported Dit on smallest equivalent oxide thickness on InGaAs substrates in the order of lower 10 to the power of 11 was reported by atomic layer deposition(ALD) of La203 on InGaAs conducted in this research. Due to prevalence of finFET design in … More recent devices structures, it is important to evaluate the characteristics of La203 interface on various orientations of InGaAs substrate. Contrary to a planar device structure, the device channel region in a FinFET device is composed of multiple orientations. Therefore, it is important to achieve high quality interface on all substrate orientations in order to benefit from the superior electrostatic gate properties of the finFET designs. In this research, MOSFETs with ALD-deposited La203 oxide on [100], [110] and [111] oriented InGaAs substrates were fabricated. All p-type substrates used in MOSFETs had pre-formed source and drain regions. It was found that a similiar Dit can be achieved on all substrates. The substhreshold swing in all MOSFETs was ~130 mV/dec which imply similar interface characteristics. However, higher drain current and transconductance values were achieved for the substrate with [111] orientation. This effect could be related to lower effective mass of electrons in this surface which is a material property of crystalline surface. These resutls show the potential for using La203 in various InGaAs devices in idustry. Less
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会议论文
Scalable La-silicate Gate Dielectric on InGaAs Substrate with High Thermal Stability and Low Interface State Densit
InGaAs 衬底上的可扩展硅酸铝栅极电介质,具有高热稳定性和低界面态密度
DOI:
--
发表时间:
2013
期刊:
影响因子:
--
作者:
[J. Naganawa, et al., Daryoush Hassan Zadeh, Daryoush Hassan Zadeh]
通讯作者:
Daryoush Hassan Zadeh
Low Dit high-k/In0.53Ga0.47As gate stack, with CET down to 0.73 nm and thermally stable silicide contact by suppression of interfacial reaction
低 Dit 高 k/In0.53Ga0.47As 栅极堆叠,CET 低至 0.73 nm,通过抑制界面反应实现热稳定硅化物接触
DOI:
10.1109/iedm.2013.6724544
发表时间:
2013
期刊:
2013 IEEE International Electron Devices Meeting
影响因子:
--
作者:
[D. Zadeh, H. Oomine, K. Kakushima, Y. Kataoka, A. Nishiyama, N. Sugii, H. Wakabayashi, K. Tsutsui, K. Natori, H. Iwai]
通讯作者:
H. Iwai