PACIFIC - Photonic Accelerator ChIp For InferenCe

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We have developed the first massively parallel photonic accelerator chip for artificial intelligence (AI) inference. Our approach is novel: amplitude modulation of light, combined with Dense Wavelength Division Multiplexing (DWDM). This combination squeezes many more computing threads into a light beam, compared to alternative solutions. Amplitude modulation also minimises signal losses, allowing us to scale even further. As a result, we can not only outperform rival tensor processing units; we can also close the gap between current performance and market need, and (crucially) continue scaling to meet future needs. Our chip is optimised for the most widely used and compute-intensive AI task: Matrix Vector Multiplication (MVM) operations. By using photonics on a standard Complementary Metal Oxide Semiconductor (CMOS) chip, we can achieve the highest possible compute density, far higher than standard CMOS electronics. A 50x50 matrix enables 1 Peta Operations Per Second (POPS) on 150 mm2.