课题基金 / 基金详情

DEVELOPMENT OF VFIF FLEXIBLE BEAM FORMER

DEVELOPMENT OF VFIF FLEXIBLE BEAM FORMER
VFIF 柔性波束形成器的开发
批准号:
6348237
负责人:
RICK TUTWILER
金额:
$20.11万
依托单位国家:
美国
项目类别:
财政年份:
2000
资助国家:
美国
项目状态:
已结题
起止时间:
2000-09-01 至 2001-08-31

项目摘要

项目成果

RICK TUTWILER的其他基金

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中文摘要
翻译
实时B型扫描的RF接收器和脉冲发生器部分 系统已设计,测试,调试,并与50 MHz换能器。 接收器部分的灵敏度为100 前端为微伏,TGC为60 dB可变增益 放大器部分(两个串联级联)。 复用和 解复用电路已经设计和测试, 目前正在集成到一个完整的2通道系统, 试验. 一旦测试了复用器和解复用器电路, 特性,RF前端电路将被复制为16 渠道 数据采集系统能够同时 在250 MHz下采样8个通道,在125 MHz下采样16个通道。 50 MHz阵列的真实的实时数字波束形成结构 设计并模拟了。 该系统是基于过采样 Σ-Δ A/D转换器技术, (波长/32)时间分辨率,用于精确的时间延迟, 和专注 Σ-Δ A/D转换器集成了 移位寄存器、多路复用器和控制逻辑, 时间延迟的适当样本。 MATLAB软件库具有 已写入分辨率,覆盖范围,时间延迟(聚焦和 转向)和采样频率。 为实现 (波长/32)分辨率,大约1GHz的采样率是 必需的. 已经定义了电路架构,并且该系统 目前正在设计的高速CMOS元件, 能够在几百MHz的工作频率下运行。
英文摘要
The RF receiver and pulser sections of a real-time B-mode scanning system have been designed, tested, debugged, and integrated with a 50 MHz transducer. The receiver section has a sensitivity of 100 microvolts on the front end and 60 dB of variable gain from the TGC amplifier sections (two are cascaded in series). Multiplexing and demultiplexing circuits have been designed and tested and are currently being integrated into a complete 2 channel system for testing. Once the mux and demux circuits are tested and characterized, the RF front end circuitry will be duplicated for 16 channels. The data acquisition system is capable of simultaneously sampling 8 channels at 250 MHz and 16 channels at 125 MHz. A real time digital beam forming architecture for a 50 MHz array has been designed and simulated. The system is based on oversampling sigma-delta A/D converter technology which samples at a (wavelength/32) time resolution for accurate time delays for steering and focusing. The sigma-delta A/D converter is integrated with a shift register, multiplexer and control logic to select the appropriate samples for the time delay. A MATLAB software library has been written for resolution , coverage, time delay (focusing and steering), and sampling frequency. In order to achieve the (wavelength/32) resolution, sampling rates on the order of 1 GHz are required. A circuit architecture has been defined and the system is currently being designed with high speed CMOS components that are capable of running at operating frequencies of several hundred MHz.
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DEVELOPMENT OF VFIF FLEXIBLE BEAM FORMER
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