课题基金 / 基金详情

DEVELOPMENT OF VFIF FLEXIBLE BEAM FORMER

DEVELOPMENT OF VFIF FLEXIBLE BEAM FORMER
VFIF 柔性波束形成器的开发
批准号:
6348237
负责人:
RICK TUTWILER
金额:
$20.11万
依托单位国家:
美国
项目类别:
财政年份:
2000
资助国家:
美国
项目状态:
已结题
起止时间:
2000-09-01 至 2001-08-31

项目摘要

项目成果

RICK TUTWILER的其他基金

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中文摘要
翻译
实时B型扫描的射频接收部分和脉冲产生部分 系统经过设计、测试、调试,并与50个 MHz换能器。接收器部分的灵敏度为100 前端为微伏,TGC的可变增益为60分贝 放大器部分(两个串联)。多路传输和 已设计和测试了多路分接电路,并 目前正在集成到一个完整的双通道系统中 测试。一旦多路复用器和多路分解器电路被测试并且 特色化,射频前端电路将复制16 频道。数据采集系统能够同时 以250 MHz采样8个通道,以125 MHz采样16个通道。 适用于50 MHz阵列的实时数字波束形成结构 进行了设计和仿真。该系统基于过采样 Sigma-Delta A/D转换器技术 (波长/32)时间分辨率,精确的转向时间延迟 集中精力。Sigma-Delta A/D转换器集成了一个 移位寄存器、多路复用器和控制逻辑 对于时间延迟的合适样本。一个MatLab软件库具有 已写入分辨率、覆盖范围、时间延迟(聚焦和 转向)和采样频率。为了实现这一目标 (波长/32)分辨率,1 GHz量级的采样率为 必填项。已经定义了电路架构,并且系统是 目前正在设计高速cmos组件,这些组件 能够在几百兆赫的工作频率下运行。
英文摘要
The RF receiver and pulser sections of a real-time B-mode scanning system have been designed, tested, debugged, and integrated with a 50 MHz transducer. The receiver section has a sensitivity of 100 microvolts on the front end and 60 dB of variable gain from the TGC amplifier sections (two are cascaded in series). Multiplexing and demultiplexing circuits have been designed and tested and are currently being integrated into a complete 2 channel system for testing. Once the mux and demux circuits are tested and characterized, the RF front end circuitry will be duplicated for 16 channels. The data acquisition system is capable of simultaneously sampling 8 channels at 250 MHz and 16 channels at 125 MHz. A real time digital beam forming architecture for a 50 MHz array has been designed and simulated. The system is based on oversampling sigma-delta A/D converter technology which samples at a (wavelength/32) time resolution for accurate time delays for steering and focusing. The sigma-delta A/D converter is integrated with a shift register, multiplexer and control logic to select the appropriate samples for the time delay. A MATLAB software library has been written for resolution , coverage, time delay (focusing and steering), and sampling frequency. In order to achieve the (wavelength/32) resolution, sampling rates on the order of 1 GHz are required. A circuit architecture has been defined and the system is currently being designed with high speed CMOS components that are capable of running at operating frequencies of several hundred MHz.
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