FaT HaMM: Fault Tolerant Hardware from Malleable Microarchitectures
FaT HaMM:可延展微架构的容错硬件
基本信息
- 批准号:2283663
- 负责人:
- 金额:--
- 依托单位:
- 依托单位国家:英国
- 项目类别:Studentship
- 财政年份:2019
- 资助国家:英国
- 起止时间:2019 至 无数据
- 项目状态:已结题
- 来源:
- 关键词:
项目摘要
Theme: Manufacturing the FutureResearch Area: Artifical Inteligence TechnologiesModern fault tolerance in electronics is built on redundancy. Foundational research in evolvable hardware has highlighted the capacity for fault tolerant systems built on flexibility; should a critical fault occur, these systems use Field Programmable Gate Arrays (FPGAs) and genetic algorithms to rewrite hardware configurations. This proposal outlines a scheme of work to develop fault resistant processors by deploying automated hardware recalibration. Two approaches will be used to mitigate the historically poor scaling of evolvable hardware. Firstly, full reconfigurability will only be used on a small scale; by embedding small regions of fully flexible hardware within a conventional inflexible processor. By replacing a number of architectural components within a processor, with counterparts built on this "malleable" microarchitecture, I aim to build the fault recovery capabilities of evolvable hardware systems into fault prone architectural components. Secondly, the flexible region will be segmented into separate zones, each an area of silicon, so that the fault can be pinpointed and only the affected region reconfigured. These steps should reduce the search space to a manageable size.The malleable microarchitectural components will consist of a mesh of FPGA-like configurable areas of hardware, and the capacity to pinpoint erroneous areas and reconfigure them, if a fault is detected. This practical flexibility will be developed in two parts; by devising tuned machine learning algorithms to compete with, or improve on, genetic algorithms, and by designing a new processor architecture using malleable microarchitectural components.Specifically, this programme of research aims to:1. Exploit modern machine learning methods to develop new automated approaches to hardware design; these approaches should be tailored to system scaling and be capable of tackling non-trivial hardware designs.2. Improve known fault models for modern processors through industrial partnerships.3. Embed FPGA technology within conventional processor designs to create a malleable hardware processor to act as a new automated hardware design substrate, with configurable degrees of flexibility.4. Create an exhaustive testing framework and explore the fault tolerance and scaling properties of the designed malleable hardware system.An initial direction for the machine learning research would explore the potential of deep learning as a mechanism of hardware logic design. Namely looking into the possibility of converting deep-learned aggressively pruned neural nets into networks of logic gates.As mentioned, one of the central problems in automated hardware design is system scaling. To tackle this; rather than try to automate the design of an entire processor, the flexible portions of the chip will be self-contained and of a manageable size; and the machine learning algorithms will be designed with scalability at the forefront.By the conclusion of this research, it is hoped that a practical fault recovery mechanism can be constructed, rivalling the current cutting edge redundancy-based methods. These processors will have the capacity to rewrite problematic fault-prone hardware to recover from performance-critical faults. Theoretical malleable processors could ship with a configuration preloaded, and out of the box they will perform identically to a conventional chip. However, upon the detection of a faulty component, a search procedure will begin to look for alternate hardware designs which reduce the impact of the fault, or negate it completely. This will result in a processor capable of a limited amount of self-healing.
主题:制造未来研究领域:电子智能技术现代电子容错是建立在冗余。可进化硬件的基础研究强调了建立在灵活性基础上的容错系统的能力;如果发生严重故障,这些系统使用现场可编程门阵列(FPGA)和遗传算法来重写硬件配置。该建议概述了一个工作计划,通过部署自动硬件重新校准来开发抗故障处理器。两种方法将被用来减轻历史上的可进化硬件的缩放差。首先,完全可重构性将仅在小规模上使用;通过在传统的不灵活的处理器内嵌入完全灵活的硬件的小区域。通过替换一个处理器内的一些架构组件,与同行建立在这个“可塑性”的微架构,我的目标是建立故障恢复能力的进化硬件系统到故障倾向的架构组件。其次,柔性区域将被分割成单独的区域,每个区域都是硅的区域,以便可以精确定位故障并且仅重新配置受影响的区域。这些步骤将把搜索空间缩小到一个可管理的大小。可延展的微架构组件将由类似FPGA的可配置硬件区域组成,并具有在检测到故障时精确定位错误区域并重新配置它们的能力。这种实际的灵活性将在两个部分中开发;通过设计调整的机器学习算法来与遗传算法竞争或改进遗传算法,以及通过使用可延展的微架构组件设计新的处理器架构。利用现代机器学习方法来开发新的硬件设计自动化方法;这些方法应针对系统扩展进行定制,并能够处理非平凡的硬件设计。通过工业伙伴关系改进现代处理器的已知故障模型。在传统的处理器设计中嵌入FPGA技术,以创建一个可延展的硬件处理器,作为一个新的自动化硬件设计基板,具有可配置的灵活性程度。4.创建一个详尽的测试框架,探索所设计的可延展硬件系统的容错性和可扩展性。机器学习研究的一个初步方向是探索深度学习作为硬件逻辑设计机制的潜力。也就是说,研究将深度学习的积极修剪神经网络转换为逻辑门网络的可能性。如上所述,自动化硬件设计的核心问题之一是系统扩展。为了解决这个问题;而不是试图自动化整个处理器的设计,芯片的灵活部分将是自包含的和可管理的大小;和机器学习算法将设计与可扩展性的最前沿。通过这项研究的结论,希望可以构建一个实用的故障恢复机制,媲美当前最先进的基于冗余的方法。这些处理器将有能力重写有问题的易出错硬件,以从性能关键故障中恢复。理论上的可延展处理器可以预装配置,开箱即用,它们的性能与传统芯片相同。然而,在检测到故障组件时,搜索过程将开始寻找减少故障影响或完全否定故障影响的替代硬件设计。这将导致处理器能够进行有限的自我修复。
项目成果
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其他文献
吉治仁志 他: "トランスジェニックマウスによるTIMP-1の線維化促進機序"最新医学. 55. 1781-1787 (2000)
Hitoshi Yoshiji 等:“转基因小鼠中 TIMP-1 的促纤维化机制”现代医学 55. 1781-1787 (2000)。
- DOI:
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LiDAR Implementations for Autonomous Vehicle Applications
- DOI:
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2021 - 期刊:
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吉治仁志 他: "イラスト医学&サイエンスシリーズ血管の分子医学"羊土社(渋谷正史編). 125 (2000)
Hitoshi Yoshiji 等人:“血管医学与科学系列分子医学图解”Yodosha(涉谷正志编辑)125(2000)。
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Effect of manidipine hydrochloride,a calcium antagonist,on isoproterenol-induced left ventricular hypertrophy: "Yoshiyama,M.,Takeuchi,K.,Kim,S.,Hanatani,A.,Omura,T.,Toda,I.,Akioka,K.,Teragaki,M.,Iwao,H.and Yoshikawa,J." Jpn Circ J. 62(1). 47-52 (1998)
钙拮抗剂盐酸马尼地平对异丙肾上腺素引起的左心室肥厚的影响:“Yoshiyama,M.,Takeuchi,K.,Kim,S.,Hanatani,A.,Omura,T.,Toda,I.,Akioka,
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