Developing a Reconfigurable On-Line Modeling Platform

描述（由申请人提供）：作为对NIMH PA-00-118的回应，本提案正在发送。该提案的目标是开始高性能可重构信号处理平台的商业化进程，该平台将执行大规模多通道数据流的实时在线分析，用于数据驱动的神经模拟和建模。该平台将用于帮助发现过程，在该过程中，感官信息在神经系统中表示和传输的合作神经编码方案将被发现。该系统将实现对神经信息流的实时解码，并且当神经信号在外围和中央处理阶段之间传输时，将实现对编码信息的实验扰动。这将在神经功能分析中提供前所未有的交互式控制，并可能导致对神经计算的生物学基础的重大见解。第一阶段提案的目的是使用高性能现场可编程门阵列（FPGA）构建一个计算节点，用于数据驱动的建模平台，并开发在高端FPGA设备中有效实现神经模型（将算法映射到硬件）所需的相关软件，以实现实时建模和仿真。这将涉及开发由赛灵思Virtex-II Pro fpga组成的原型板，该fpga在节点之间具有足够的通信带宽，以确保实时性能。我们将探讨几种实现技术，以发现在硬件中实现神经建模算法的最有效方法。这些方法包括：1.)使用Mathwork的Matlab/Simulink和Xilinx的System Generator将Simulink的框图映射到硬件。2.） 使用Xilinx的FORGE编译器将JAVA代码转换为硬件。3)。使用Celoxica的C编译器将C代码转换为硬件。4)。在fpga中开发和嵌入自定义神经微处理器。

DESCRIPTION (provided by applicant): This proposal is being sent in response to NIMH PA-00-118. The objective of this proposal is to begin the commercialization process of a high performance reconfigurable signal-processing platform that will perform real-time on-line analysis of large-scale multi-channel data streams for data-driven neural simulations and modeling. The platform will be used to aid the discovery process where the cooperative neural encoding schemes through which sensory information is represented and transmitted within a nervous system will be uncovered. The system will enable real-time decoding of the neural information streams, and will enable experimental perturbation of the encoded information while the neural signals are in transit between peripheral and central processing stages. This will provide an unprecedented degree of interactive control in the analysis of neural function, and could lead to major insights into the biological basis of neural computation. The aim of this Phase I proposal is to construct a computation node using high performance field programmable gate arrays (FPGA) to be used in a data-driven modeling platform and to develop the associated software necessary to implementing neural models (mapping algorithms to hardware) efficiently in high end FPGA devices to enable real-time modeling & simulations. This will involve developing prototype boards comprised of Xilinx's Virtex-II Pro FPGAs with adequate communication bandwidth between nodes to ensure real-time performance. Several implementation techniques will be explored to discover the most efficient method of implementing neural modeling algorithms in hardware. These methods include: 1.) Using Mathwork's Matlab/Simulink and Xilinx's System Generator to map Simulink block diagrams to hardware. 2.) Using Xilinx's FORGE compiler to translate JAVA code to hardware. 3.) Using Celoxica's C Compiler to translate C code to hardware. 4.) Developing and embedding custom neural microprocessors in FPGAs.