III-V quantum dot lasers grown on patterned silicon and SOI substrates by MBET first year

为了获得高效的光电子光源和高迁移率的电子器件，人们迫切需要在硅平台上集成III-V材料和器件。然而，直接外延生长面临着巨大的挑战，包括反相界(APB)、穿线位错(TDS)和微裂纹。在过去的几年里，通过几个微米的III-V缓冲层在减少这三种类型的缺陷方面取得了重大进展。此外，由于III-V外延层和硅衬底之间的热膨胀不匹配，III-V层的总厚度被限制在几个微米(&lt；6um)，这是由于形成了微裂纹。在这个项目中，我们将利用图案化硅的潜力来抑制硅或SOI衬底上图案化区域内的缺陷形成。最重要的是，我们希望通过在UCL使用双分子束外延系统在图案化区域内生长第四类材料，如Si和Ge来生长纳米尺寸的空穴，以缓解III-V层与硅衬底之间的应变，从而解决III-V层与硅衬底之间热膨胀不匹配的问题。

There is a strong demand for integrating of III-V materials and devices on silicon platform for high-efficient photonics light sources and high mobility electronics devices. However, there are significant challenges for direct epitaxial growth, including anti-phase boundaries (APBs), threading dislocations (TDs) and micro-cracks. In last few years, significant progress has been made in reducing these three types of defects with a few micrometre III-V buffer layers. In addition, the total thickness of III-V layers is limited to a few micrometres (< 6um) by the formation of micro-cracks due to a mismatch in thermal expansion between the III-V epilayers and a Si substrate. In this project, we will exploit the potential of patterned silicon to suppress the defect formation within the patterned area on Si or SOI substrates. Most importantly, we would like to grow nano-size holes within the patterned areas by grow group-IV materials, such as Si and Ge by using twin-MBE system at UCL to relax the strain between III-V layers and silicon substrates, and hence to solve the problem due to thermal expansion mismatch between III-V layers and silicon substrates.