Hard-Middleware: Facilitating Reliable Machine Learning Deployment for Automotive Applications

随着晶体管规模的不断扩大，性能和能源效率不断提高，电子设备对大气辐射的敏感性也越来越受到关注。这种辐射会导致设备故障。系统的可靠性越来越受到人们的重视，特别是对于自动驾驶等安全关键应用。这些对安全至关重要的应用，特别是在汽车领域，通常以机器学习任务为特征，例如物体检测。这类应用程序的性能和可靠性要求各不相同，并且经常随时间变化。通常，应用程序是通过将通用硬件（软件）转换为定制电路（硬件）来加速的。与传统的基于软件的方法相比，这可以提供巨大的速度提升。在汽车领域越来越受关注的定制硬件平台之一是fpga（现场可编程门阵列）。这种类型的平台允许用户利用定制硬件的好处，而不需要生产定制硅的大量非经常性工程成本。辐射会对fpga造成许多问题。总电离剂量（Total Ionising Dose，简称TID）是一种高能粒子，它会造成电路级的损伤，使用抗辐射设备可以大大降低这种影响。但是，必须使用SEU缓解技术来处理导致存储单元逻辑状态翻转的高能粒子SEU（单事件扰动）的影响。我们建议创建一个虚拟硬件或覆盖层，称为“硬中间件”，作为用户应用程序和将在其上执行的FPGA平台之间的中介。而不是直接编程的FPGA，我们提出的目标是这个虚拟硬件。然后在物理硬件上实现覆盖。这将允许体系结构动态地适应不断变化的应用程序需求和环境条件。这样就可以在不影响应用程序设计的情况下平衡性能和效率与可靠性。然后，用户可以指定覆盖层将提供的服务质量。对于给定的应用程序，可以单独且透明地考虑可靠性需求。覆盖层将利用现有的加固方法来实现给定应用程序所需的可靠性级别。CGRAs（粗粒度可重构阵列）是通用处理器和定制电路之间的中间地带。与fpga的位级操作相比，硬件被组织成一组可以执行字级操作的处理元素。由于计算单元的粗粒度特性，CGRA的配置速度比FPGA快得多。我们将使用CGRA作为我们的虚拟硬件。用户将在更高的级别上定位此架构，而架构本身将映射到低级别的FPGA。保护机制将在CGRA和FPGA之间提供，这意味着用户只需要将他们的应用程序映射到CGRA。使用这种类型的体系结构使我们能够利用关注CGRAs开发的已有研究，并将精力集中在提供用户无需详细考虑的自动性能-可靠性权衡上。在汽车领域部署现代机器学习应用程序将促进自动驾驶系统能力的逐步变化。虽然我们的研究主要集中在汽车领域，但面对越来越不可靠的硬件，它将对高可靠性计算的延续有更广泛的好处。

As transistor scaling continues to push for greater performance and energy efficiency, the susceptibility of electronic devices to atmospheric radiation is of greater concern. Such radiation can cause failure within a device. The reliability of a system is of increasing consideration, especially for safety-critical applications such as autonomous driving. These safety-critical applications, particularly in the automotive sector, often feature machine learning tasks, such as object detection. Performance and reliability requirements of such applications are varied and often change over time. Normally, applications are accelerated through the translation of general-purpose hardware (software) to bespoke circuitry (hardware). This can provide huge speed-ups over conventional software-based approaches. One such class of platforms for custom hardware that is of growing interest in the automotive sector are FPGAs (Field-Programmable Gate Arrays). This type of platform allows users to exploit the benefits of custom hardware without the large non-recurring engineering cost of producing custom silicon.Radiation can cause numerous problems on FPGAs. Effects such as TID (Total Ionising Dose), high energy particles that causes circuit-level damage, have been vastly reduced using radiation-hardened devices. However, the effects of SEUs (Single Event Upsets), high-energy particles that cause the logical state of a memory cell to flip, must be handled using SEU mitigation techniques.We propose the creation of a virtual hardware, or overlay, dubbed "Hard-Middleware" to act as an intermediary between the user's application and the FPGA platform it will execute on. Rather than programming the FPGA directly, we propose the targeting of this virtual hardware. The overlay will then be realised on physical hardware. This will allow the architecture to adapt dynamically to changing application requirements and environmental conditions. Performance and efficiency can then be balanced with reliability without affecting the design of the application. The user can then specify qualities of service that the overlay will then deliver. For a given application, the reliability requirements can be considered separately and transparently. The overlay will utilise existing hardening methodologies to realise the required level of reliability for a given application. CGRAs (Coarse Grain Reconfigurable Arrays) are a middle ground between general-purpose processors and bespoke custom circuitry. Hardware is organised into an array of processing elements that can perform word-level operations, compared with FPGAs bit-level operations. Due to the coarse-grained nature of the compute units, a CGRA can be configured much faster than an FPGA. We will use a CGRA as our virtual hardware. The user will target this architecture at a higher level, while the architecture itself will be mapped to an FPGA at a low-level. Protection mechanisms will be provided between the CGRA and the FPGA, meaning that the user need only map their application to the CGRA. Using this type of architecture allows us to draw on the pre-existing research that has focused on the development of CGRAs and focus our efforts on providing an automatic performance-reliability trade-off that the user need not consider in detail. Enabling the deployment of modern machine learning applications in the automotive sector will facilitate a step change in the capability of autonomous driving systems. Although our research focuses on the automotive sector, it will be of wider benefit to the continuation of high-reliability computation in the face of increasingly unreliable hardware.