Hard-Middleware: Facilitating Reliable Machine Learning Deployment for Automotive Applications

硬件中间件：促进汽车应用的可靠机器学习部署

• 批准号: 2481244
• 金额: --
• 依托单位: Imperial College London
• 依托单位国家: 英国
• 项目类别: Studentship
• 财政年份: 2020
• 资助国家: 英国
• 起止时间: 2020 至 无数据
• 项目状态: 已结题
• 来源: https://gtr.ukri.org/projects?ref=studentship-2481244
• 关键词: Hard; Middleware; Facilitating; Reliable; Machine

As transistor scaling continues to push for greater performance and energy efficiency, the susceptibility of electronic devices to atmospheric radiation is of greater concern. Such radiation can cause failure within a device. The reliability of a system is of increasing consideration, especially for safety-critical applications such as autonomous driving. These safety-critical applications, particularly in the automotive sector, often feature machine learning tasks, such as object detection. Performance and reliability requirements of such applications are varied and often change over time. Normally, applications are accelerated through the translation of general-purpose hardware (software) to bespoke circuitry (hardware). This can provide huge speed-ups over conventional software-based approaches. One such class of platforms for custom hardware that is of growing interest in the automotive sector are FPGAs (Field-Programmable Gate Arrays). This type of platform allows users to exploit the benefits of custom hardware without the large non-recurring engineering cost of producing custom silicon.Radiation can cause numerous problems on FPGAs. Effects such as TID (Total Ionising Dose), high energy particles that causes circuit-level damage, have been vastly reduced using radiation-hardened devices. However, the effects of SEUs (Single Event Upsets), high-energy particles that cause the logical state of a memory cell to flip, must be handled using SEU mitigation techniques.We propose the creation of a virtual hardware, or overlay, dubbed "Hard-Middleware" to act as an intermediary between the user's application and the FPGA platform it will execute on. Rather than programming the FPGA directly, we propose the targeting of this virtual hardware. The overlay will then be realised on physical hardware. This will allow the architecture to adapt dynamically to changing application requirements and environmental conditions. Performance and efficiency can then be balanced with reliability without affecting the design of the application. The user can then specify qualities of service that the overlay will then deliver. For a given application, the reliability requirements can be considered separately and transparently. The overlay will utilise existing hardening methodologies to realise the required level of reliability for a given application. CGRAs (Coarse Grain Reconfigurable Arrays) are a middle ground between general-purpose processors and bespoke custom circuitry. Hardware is organised into an array of processing elements that can perform word-level operations, compared with FPGAs bit-level operations. Due to the coarse-grained nature of the compute units, a CGRA can be configured much faster than an FPGA. We will use a CGRA as our virtual hardware. The user will target this architecture at a higher level, while the architecture itself will be mapped to an FPGA at a low-level. Protection mechanisms will be provided between the CGRA and the FPGA, meaning that the user need only map their application to the CGRA. Using this type of architecture allows us to draw on the pre-existing research that has focused on the development of CGRAs and focus our efforts on providing an automatic performance-reliability trade-off that the user need not consider in detail. Enabling the deployment of modern machine learning applications in the automotive sector will facilitate a step change in the capability of autonomous driving systems. Although our research focuses on the automotive sector, it will be of wider benefit to the continuation of high-reliability computation in the face of increasingly unreliable hardware.

随着晶体管尺寸不断缩小以提高性能和能源效率，电子设备对大气辐射的敏感性越来越受到关注。这种辐射可能会导致设备内部发生故障。系统的可靠性越来越受到重视，特别是对于自动驾驶等安全关键型应用。这些安全关键型应用，特别是在汽车领域，通常具有机器学习任务，例如物体检测。此类应用的性能和可靠性要求各不相同，并且经常随时间而变化。通常，通过将通用硬件（软件）转换为定制电路（硬件）来加速应用程序。与传统的基于软件的方法相比，这可以提供巨大的加速。 FPGA（现场可编程门阵列）是汽车行业越来越感兴趣的一类定制硬件平台。这种类型的平台允许用户充分利用定制硬件的优势，而无需花费大量非经常性工程成本来生产定制芯片。辐射可能会导致 FPGA 出现许多问题。使用抗辐射设备可以大大减少诸如 TID（总电离剂量）和导致电路级损坏的高能粒子等效应。然而，SEU（单事件翻转）（导致存储单元逻辑状态翻转的高能粒子）的影响必须使用 SEU 缓解技术来处理。我们建议创建一个虚拟硬件或覆盖层，称为“硬件中间件”，充当用户应用程序和它将执行的 FPGA 平台之间的中介。我们建议以该虚拟硬件为目标，而不是直接对 FPGA 进行编程。然后覆盖将在物理硬件上实现。这将使架构能够动态适应不断变化的应用程序需求和环境条件。然后可以在性能和效率与可靠性之间取得平衡，而不会影响应用程序的设计。然后，用户可以指定覆盖层将提供的服务质量。对于给定的应用，可以单独且透明地考虑可靠性要求。该覆盖层将利用现有的强化方法来实现给定应用程序所需的可靠性水平。 CGRA（粗粒可重构阵列）是通用处理器和定制电路之间的中间立场。与 FPGA 的位级操作相比，硬件被组织成可以执行字级操作的处理元件阵列。由于计算单元的粗粒度性质，CGRA 的配置速度比 FPGA 快得多。我们将使用 CGRA 作为我们的虚拟硬件。用户将在更高级别上针对该架构，而架构本身将在低级别上映射到 FPGA。 CGRA和FPGA之间将提供保护机制，这意味着用户只需将其应用程序映射到CGRA即可。使用这种类型的架构使我们能够利用专注于 CGRA 开发的现有研究，并将我们的精力集中在提供用户无需详细考虑的自动性能与可靠性权衡上。在汽车领域部署现代机器学习应用将促进自动驾驶系统能力的阶跃变化。虽然我们的研究重点是汽车领域，但面对日益不可靠的硬件，继续进行高可靠性计算将会有更广泛的好处。