Efficient Application Mapping for Massively Parallel Systems

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Massive parallel compute architectures such as GPUs and FPGAs are becoming increasingly popular, as they offer greater parallelism capabilities and more application-specific processing capability, compared to traditional high-performance computing approaches. Graph-based problems are particularly amenable to massive parallelism: a large number of small processing elements performing simple computation, that interact with each other using small messages.Despite the ubiquity of graph-based massive parallel problems, determining how to map such problems onto hardware remains a largely unexplored problem, in part because hardware has only recently become available able to support the truly massive parallelism. This is a major research opportunity in the development of efficient, general-purpose mapping algorithms for parallel systems that can start from an abstract graph representation of the problem and produce a hardware graph representing the problem as mapped to the physical hardware.