Efficient Application Mapping for Massively Parallel Systems

与传统的高性能计算方法相比，大规模并行计算体系结构(如GPU和FPGA)正变得越来越受欢迎，因为它们提供了更强的并行能力和更特定于应用的处理能力。基于图的问题特别容易受到大规模并行的影响：大量执行简单计算的小型处理元素使用小消息彼此交互。尽管基于图的大规模并行问题无处不在，但确定如何将这些问题映射到硬件上在很大程度上仍然是一个未被探索的问题，部分原因是硬件最近才能够支持真正的大规模并行。这是开发用于并行系统的高效、通用映射算法的主要研究机会，该算法可以从问题的抽象图表示开始，并产生表示映射到物理硬件的问题的硬件图。

Massive parallel compute architectures such as GPUs and FPGAs are becoming increasingly popular, as they offer greater parallelism capabilities and more application-specific processing capability, compared to traditional high-performance computing approaches. Graph-based problems are particularly amenable to massive parallelism: a large number of small processing elements performing simple computation, that interact with each other using small messages.Despite the ubiquity of graph-based massive parallel problems, determining how to map such problems onto hardware remains a largely unexplored problem, in part because hardware has only recently become available able to support the truly massive parallelism. This is a major research opportunity in the development of efficient, general-purpose mapping algorithms for parallel systems that can start from an abstract graph representation of the problem and produce a hardware graph representing the problem as mapped to the physical hardware.