A comparison of AArch64 and RISC-V through accurate simulation

通过精确仿真比较AArch64和RISC-V

• 批准号: 2767177
• 金额: --
• 依托单位: University of Bristol
• 依托单位国家: 英国
• 项目类别: Studentship
• 财政年份: 2022
• 资助国家: 英国
• 起止时间: 2022 至 无数据
• 项目状态: 未结题
• 来源: https://gtr.ukri.org/projects?ref=studentship-2767177
• 关键词: comparison; AArch64; RISC; through; accurate

This project falls under the EPSRC architectures and operating systems research area.Arm's AArch64 instruction set architecture (ISA) is currently establishing itself as a key alternative to x86 systems in the high performance computing (HPC) and cloud fields. This is most notably seen by its recent use in the A64FX chip, used within Fugaku, the most powerful supercomputer in the world up until June 2022 [1]. As a reduced instruction set computer (RISC), a natural competitor is RISC-V. Having been recently developed at UC Berkley, this open source ISA is starting to gain traction for use in real world applications due to it being simple, free to use, and open to modification, all features not provided by Arm's instruction set. Large technology companies such as Google and Amazon are now moving towards the use of their own, in-house silicon for use in their cloud data centres. One of the first and most fundamental decisions to be made when designing these systems is the ISA, as this can affect every other part of a chip's microarchitecture. But currently, there is no objective data comparing multiple instruction sets, meaning these decisions must be made using more subjective metrics rather than hard evidence. One of the initial aims of my research is to gain objective data allowing for a fair comparison of AArch64 and RISC-V. Firstly, I will conduct experiments into the instruction counts needed to run a range of HPC codes targeted by many commonly used compilers. As a follow up to this, I will determine if this difference in instruction count effects the time taken to run these codes on modern, high performance, out of order, superscalar processors. To do this, I will help develop SimEng [2]; a fast, accurate, easily modifiable, open source processor simulator currently in development by the University of Bristol HPC research group. A simulator with all of these qualities has, up until now, not been openly available. Currently, within the field, there are two alternatives for accurate processor simulation: in-house simulators, which do not provide easily reproducible results; or Gem5 [3], which is often hard to modify and has slow simulation times. SimEng addresses these issues, allowing for easily gained and reproducible results. My aim is to set up a simulation using the same microarchitectural backend with different front ends for each respective ISA. Running many different codes compiled to each ISA through this simulation will provide a fair comparison of the two ISAs when implemented in modern state-of-the-art processors. An experiment that, without SimEng, would have been very difficult to conduct but will provide invaluable data for tech companies informing their decisions about the next generation of cloud and HPC systems.This work is partially funded by Huawei, who are helping to support rv32 within SimEng.1. [online] https://www.top500.org/lists/top500/2021/11/2. [online] https://github.com/UoB-HPC/SimEng3. [online] https://www.gem5.org/

该项目属于EPSRC架构和操作系统研究领域。Arm的AArch64指令集架构（ISA）目前正在高性能计算（HPC）和云计算领域成为x86系统的关键替代品。最明显的是它最近在A64FX芯片上的使用，该芯片在2022年6月之前是世界上最强大的超级计算机Fugaku中使用。作为精简指令集计算机（RISC）， RISC- v是一个自然的竞争对手。这个开源的ISA最近是在加州大学伯克利分校开发的，由于它简单、免费使用、允许修改，所有这些特性都是Arm指令集没有提供的，因此它开始在现实世界的应用程序中得到应用。b谷歌和亚马逊（Amazon）等大型科技公司现在正朝着使用自己的内部芯片用于云数据中心的方向发展。在设计这些系统时，首先要做的最基本的决定之一是ISA，因为它会影响芯片微体系结构的其他部分。但目前，还没有比较多个指令集的客观数据，这意味着这些决策必须使用更多的主观指标，而不是确凿的证据。我研究的最初目的之一是获得客观数据，以便对AArch64和RISC-V进行公平比较。首先，我将对运行许多常用编译器针对的一系列HPC代码所需的指令计数进行实验。接下来，我将确定指令计数的差异是否会影响在现代、高性能、无序、超标量处理器上运行这些代码所花费的时间。要做到这一点，我将帮助发展四盟b[2]；一个快速、准确、易于修改的开源处理器模拟器，目前由布里斯托尔大学HPC研究小组开发。到目前为止，还没有一个具有所有这些特性的模拟器可以公开使用。目前，在该领域，有两种方法可以实现精确的处理器模拟：内部模拟器，它不能提供容易重复的结果；或Gem5[3]，它通常难以修改并且模拟时间较慢。思梦解决了这些问题，允许轻松获得和可重复的结果。我的目标是为每个ISA使用相同的微架构后端和不同的前端来设置模拟。通过此模拟运行编译到每个ISA的许多不同代码，将在现代最先进的处理器中实现这两个ISA时提供一个公平的比较。如果没有思梦，这项实验将很难进行，但它将为科技公司提供宝贵的数据，为他们决定下一代云和高性能计算系统提供信息。这项工作部分由华为资助，华为正在帮助支持SimEng.1中的rv32。[网络]https://www.top500.org/lists/top500/2021/11/2。[网络]https://github.com/UoB-HPC/SimEng3。[网络]https://www.gem5.org/