A High-level Design Environment for the Rapid FPGA Implementations of Deep Learning Architecture

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Artificial Intelligence (AI) is becoming the default choice for many of the applications in the industries such as image processing and pattern recognition. As a result, there has been a great deal of work on developing and implementing AI algorithms in both industry and academia, using convenient frameworks like TensorFlow and PyTorch. These frameworks work fine on both CPU and GPU platforms. However, when there are strict power requirements, GPU and CPUs cannot provide enough power efficiency and FPGAs will be used for running the inference of the AI applications. Unfortunately, those frameworks are not compatible with the design environment of FPGAs as users are required to use Hardware Description Languages (HDL) in Register Transfer Level (RTL) to implement designs to FPGAs. Even with the vendor's recent High-level Synthesis (HLS) tools, which allow users to use C/C++ instead of RTL, the AI applications are too complex to implement within a short period. Thus, the aim of this project is to deliver a true high-level environment for AI developers to rapidly implement their AI applications on FPGAs using Python, the most common language in the world of AI development, without any hardware knowledge. AI developers can implement their AI applications on FPGAs just as easy as PC.