Low-Power Programmable Switch Architecture

现在，如何通过低功耗设计来降低数字集成电路的功耗已经成为后摩尔时代最重要的问题之一。这一问题在可编程开关领域尤为重要。由于部署的交换机数量巨大，单个交换机的功耗略有增加将导致整个网络的总功耗大幅增加，反之亦然。因此，通过低功耗设计降低总功耗的效果是可观的，对减少碳排放的贡献是不言而喻的。协议无关交换体系结构(PISA)是研究界使用的主流可编程交换体系结构。它在匹配域和分组处理操作方面具有优势，以及软件定义网络操作的更高灵活性。然而，PISA体系结构由于其工作原理，在功耗性能上存在固有缺陷，不能直接支持低功耗设计技术。此外，大多数基于体系结构的研究都集中在改进性能或功能上。很少有研究在功耗性能和与低功耗设计技术的兼容性方面取得重大进展。因此，为了实现低功耗设计技术，降低功耗，提出一种新的可编程开关体系结构可以被认为是一种可行的解决方案。本研究的重点是设计一种新型的可编程开关体系结构，该体系结构可以在保持与当前主流体系结构PISA相似或更好的性能的同时，降低可编程开关的功耗。具体可分为三个部分：1.设计了一种新的可编程开关体系结构，能够实现低功耗设计技术，避免了PISA在功耗方面的缺陷。研究新架构下先进的低功耗设计技术动态频率和电压调节(DVFS)。为新的体系结构开发编译器和开发工具在PISA体系结构中，用于处理包的流水线仅在软件级别被分成多个阶段。然而，这可能会导致硬件资源和功耗的浪费。因此，我们可以通过设计一种新的体系结构，在硬件层面上将这两个阶段分开，只在形成流水线时使用所需的阶段。这种设计还允许新的架构使用低功耗设计技术来降低功耗。例如，使用时钟门控和功率门控来完全关闭未使用的级。DVFS是最强大的低功耗设计技术之一。它可以随着业务量的变化而改变交换机的工作频率和电压，以实现最小的功耗。然而，流量的变化是无法预测的。如果DVFS只使用流量作为指标，开关频率和电压的频繁变化将导致更多的功耗浪费。因此，目前还没有关于DVFS在可编程开关中应用的研究。本研究将通过改进新的体系结构，在可编程交换机上实现DVFS。通过控制平面在宏观层面对流量进行监控，并对流量切换策略进行约束，实现流量预测，降低了交换机的功耗，提高了交换机的能效。此外，为了便于未来研究和社区使用新架构，有必要为新架构设计编译器和相应的开发工具(软件包、软件框架、可视化编程)。所有这些工具都将是开源的，可以降低开发新架构的学习成本，使新架构得到更广泛的应用。本项目属于EPSRC ICT网络和分布式系统研究领域。

Now, how to reduce the power consumption of digital integrate circuit through low-power design has become one of the most important problems in the post-Moore era. This problem is particularly important in the field of programmable switch. Due to the enormous number of switches deployed, a slight increase in the power consumption of a single switch will lead to a significant increase in the total power consumption of the whole network and vice versa. Therefore, the effect of reducing total power consumption through low-power design is substantial, and the contribution to reducing carbon emissions is self-evident.Protocol Independent Switching Architecture (PISA) is the mainstream programmable switch architecture used in the research community. It has superiority in matching fields and packet processing operations, as well as higher flexibility of Software Defined Network operations. However, PISA architecture has inherent defects in power consumption performance due to its working principle and cannot enable low power design technologies directly. In addition, most architecture-based research focuses on improving performance or function. Few research has made significant advances in power consumption performance and compatibility with low-power design technologies. Therefore, to enable low-power design technologies and reduce power consumption, the proposal of a new programmable switch architecture can be regarded as a feasible and promising solution.This research focuses on designing a novel programmable switch architecture that can reduce the power consumption of programmable switches while maintaining similar or better performance compared to the current mainstream architecture PISA. Specifically, it can be divided into three parts:1. Design a new programmable switch architecture that can enable low-power design technologies and avoid the drawbacks of PISA in terms of power consumption.2. Investigate the advanced low power design technology Dynamic Frequency and Voltage Scaling (DVFS) on new architecture.3. Develop the compiler and development tools for new architectureIn the PISA architecture, the pipeline used to process packages is divided into multiple stages only at the software level. However, this can lead to waste of hardware resources and power consumption. Therefore, we can separate these stages at the hardware level by designing a new architecture, and only use the required stages when forming the pipeline. This design also allows the new architecture to use low-power design technologies to reduce the power consumption. For example, using clock gating and power gating to completely shut down the unused stages.DVFS is one of the most powerful low-power design technologies. It can change the operating frequency and voltage of the switch with changes in traffic to achieve the minimum power consumption. However, changes in traffic cannot be predicted. If DVFS only uses traffic as an indicator, frequent changes in frequency and voltage of the switch will result in more waste of power consumption. Therefore, there is currently no research focuses on the application of DVFS in programmable switches. This research will implement DVFS in programmable switches by improving the new architecture. And predict traffic by monitoring traffic at the macro level through control planes, as well as constraining traffic switching strategies, to reduce power consumption and increase power efficiency of the switch.Besides, to facilitate the use of new architecture for future research and community, it is necessary to design a compiler and corresponding development tools (Software package, software framework, visual programming) for new architecture. All these tools will be open source, which can reduce the learning cost for the development of new architecture and make the new architecture more widely used.This project falls within the EPSRC ICT networks and distributed systems research area.