Advanced Design, Partitioning and Test for System-in-Package Electronics

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The ADEPT-SiP project is directed at the development and demonstration of a rigorous, right-first-time design and supply chain management methodology for novel System-in-Package Electronics Product Functions. The project will address schematic capture, partitioning and active device, substrate and package design to meet specific performance, cost, size and weight targets. Other key design stages will include thermal and EMC design, and design-for-manufacture, test, reliability and for environmental impact. Novel, high density embedded passive substrate technologies will be designed and simulated, process characterisation undertaken and parameterised component models developed for the full range of passive components and interconnection and assembly structures. The core design, simulation and modelling activities will be proven in System-in-Package technology demonstrators.