Methods for the design and testing of digital systems

主要研究领域涉及有限状态机的设计和使用，作为生成器构建在芯片上，以提供芯片上系统的内置自检。我们提出了元胞自动机寄存器(CAR)作为线性反馈移位寄存器在许多应用中的替代方案，因为虽然从理论角度看它们类似于线性反馈移位寄存器，但它们生成的位序列导致了测试行为的改善。我们早期的工作已经产生了用于综合这些机器的唯一实用算法。然而，很明显，将它们修改为稍微非线性，可以提高测试性能。这类机器的设计和分析要复杂得多，因为我们缺乏一些分析工具，而且拟议的研究将随着CAR的发展和对其他非线性机器的基础研究而继续进行。我们的第二个方向是去年在可逆逻辑领域发展的一个新方向。它借鉴了我们25年前在电路设计的受限原语方面的一些早期工作。最近，由于冯·诺依曼/兰道尔原理，即正常(不可逆)逻辑运算产生基本的最小能量成本，这一点变得越来越重要。这一成本可能会在未来15到20年内终止实际计算机性能的改进。然而，事实证明，基于可逆逻辑运算的计算机可以重复使用一小部分信号能量(理论上，这一比例可以接近100%)，这给了我们在指定的功耗水平下继续任意提高计算机性能的可能性。要做到这一点，我们必须开发用于设计和测试高度优化的可逆逻辑电路的算法。这是我们第二个研究领域的目标。

The major area of study concerns the design and uses of Finite State Machines as generators to build onto a chip to provide built-in self-testing of the system on the chip. We have proposed Cellular Automata Registers (CAR) as alternatives to linear feedback shift registers in a number of applications, since, while they are similar to linear feedback shift registers from a theoretical perspective, they generate bit sequences that lead to improved testing behaviour. Our earlier work has led to the only practical algorithm for the synthesis of these machines. However, it is clear that modifying them to be slightly non-linear, gives improved performance for testing. The design and analysis of such machines is considerably more complex, since we lack some of the analytical tools, and the proposed research will continue both with the development of CAR and underlying research into other non linear machines. Our second direction is a new one developed over the last year in the area of reversible logic.  It picks up on some of our earlier work from 25 years ago on restricted primitives for the design of circuits. This are has become of rapidly increasing importance rcently because of the von Neumann/Landauer principle that normal (non reversible) logic operations incur a fundamental minimum energy cost. This cost threatens to end improvements in practical computer performance within the next 15 to 20 years. However, it has been proved that computers based on reversible logic operations can reuse a fraction of the signal energy (in theory, this fraction can approach 100%) that gives us the possibility of continuing to arbitrarily improve computer performance within a specified level of power dissipation. For this to be feasible, we have to develop algorithms for the design and testing of highly optimized reversible logic circuits. This is the goal of our second research area.