Building error-resilient applications on many-core platforms

在多核平台上构建容错应用程序

• 批准号: 386463-2010
• 负责人: Pattabiraman, Karthik
• 金额: $ 1.82万
• 依托单位: University of British Columbia
• 依托单位国家: 加拿大
• 项目类别: Discovery Grants Program - Individual
• 财政年份: 2012
• 资助国家: 加拿大
• 起止时间: 2012-01-01 至 2013-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=508202
• 关键词: Building; error; resilient; applications; many

Emerging applications demand increasing amounts of computational power, which cannot be satisfied by today's micro-processors. To keep up with this demand, many-core processors with tens or hundreds of cores will soon become a reality. However, many-core processors will experience high rates of hardware errors, due to the fundamental limits of physics and engineering. Traditional approaches that mask hardware errors from software incur high power-overheads, which limit their applicability in many-core processors. Therefore, future applications must be capable of anticipating and tolerating hardware errors in order to leverage the computational capacities of many-core platforms.

新兴的应用需要越来越多的计算能力，这是今天的微处理器无法满足的。为了跟上这一需求，数十核或数百核的多核处理器将很快成为现实。然而，由于物理和工程的基本限制，多核处理器将经历高硬件错误率。从软件中屏蔽硬件错误的传统方法会招致高功率开销，这限制了它们在多核处理器中的适用性。因此，未来的应用程序必须能够预测和容忍硬件错误，以便利用多核平台的计算能力。