Computer-Aided Design for High-Performance Large-Scale Integrated Circuits

高性能大规模集成电路的计算机辅助设计

• 批准号: RGPIN-2015-03759
• 负责人: Najm, Farid
• 金额: $ 2.7万
• 依托单位: University of Toronto
• 依托单位国家: 加拿大
• 项目类别: Discovery Grants Program - Individual
• 财政年份: 2015
• 资助国家: 加拿大
• 起止时间: 2015-01-01 至 2016-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=589361
• 关键词: Computer; Aided; Design; Performance; Large

In order to enable the design of future advanced large-scale integrated circuits (ICs), we are developing computer-aided design (CAD) tools and techniques to address a number of challenges relating to the verification, optimization, and design of the chip power distribution network (PDN), also simply referred to as the power grid. With increased power dissipation and reduced supply voltage, large microprocessors today draw over 150 Amperes from the external supply! These levels of current are unprecedented in microelectronics, and are a key challenge for design. Apart from the design issues of delivering well-regulated low voltages at these extremes of current, a key problem for designers is to make sure that the increased voltage drop and/or rise (due to IR-drop and/or Ldi/dt drop) in the chip PDN do not lead to circuit delay errors and functional failures. However, checking the grid node voltages is very time-consuming and expensive, so that it is often incompletely done, or not done at all. We have worked for the last decade on power grid verification, but we now propose to embark on an innovative new research direction to develop new techniques for enabling verification, design and optimization of the power grid. This new direction involves solving the inverse of the traditional verification problem: instead of asking users to provide the circuit currents and reporting to them whether or not the grid is safe, we simply tell them what ranges or combinations of circuit currents would be guaranteed to maintain grid safety. There are many advantages for this approach, such as large improvements in the speed of verification, as well as valuable information for design placement and floorplanning regarding the locations on the chip where high power blocks may be placed.

为了能够设计未来先进的大规模集成电路(IC)，我们正在开发计算机辅助设计(CAD)工具和技术，以应对与芯片配电网络(PDN)(也简称为电网)的验证、优化和设计相关的许多挑战。随着功耗的增加和电源电压的降低，今天的大型微处理器从外部电源中消耗了超过150安培的电流！这种电流水平在微电子领域是史无前例的，也是设计的关键挑战。除了在这些极端电流下提供调节良好的低电压的设计问题外，设计者面临的一个关键问题是确保芯片PDN中增加的电压下降和/或上升(由于IR下降和/或LDI/DT下降)不会导致电路延迟错误和功能故障。然而，检查电网节点电压是非常耗时和昂贵的，因此它经常不完全完成，或者根本没有完成。我们在过去的十年里一直致力于电网验证，但现在我们建议开始一个创新的新研究方向，以开发新的技术来实现电网的验证、设计和优化。这个新的方向涉及到解决传统验证问题的逆问题：我们不是要求用户提供电路电流并向他们报告电网是否安全，而是只需告诉他们保证电网安全的电路电流范围或组合。这种方法有许多优点，例如验证速度的大幅提高，以及关于芯片上可能放置高功率模块的位置的设计布局和布局规划的有价值的信息。