Computer-Aided Design for High-Performance Large-Scale Integrated Circuits

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In order to enable the design of future advanced large-scale integrated circuits (ICs), we are developing computer-aided design (CAD) tools and techniques to address a number of challenges relating to the verification, optimization, and design of the chip power distribution network (PDN), also simply referred to as the power grid. With increased power dissipation and reduced supply voltage, large microprocessors today draw over 150 Amperes from the external supply! These levels of current are unprecedented in microelectronics, and are a key challenge for design. Apart from the design issues of delivering well-regulated low voltages at these extremes of current, a key problem for designers is to make sure that the increased voltage drop and/or rise (due to IR-drop and/or Ldi/dt drop) in the chip PDN do not lead to circuit delay errors and functional failures. However, checking the grid node voltages is very time-consuming and expensive, so that it is often incompletely done, or not done at all. We have worked for the last decade on power grid verification, but we now propose to embark on an innovative new research direction to develop new techniques for enabling verification, design and optimization of the power grid. This new direction involves solving the inverse of the traditional verification problem: instead of asking users to provide the circuit currents and reporting to them whether or not the grid is safe, we simply tell them what ranges or combinations of circuit currents would be guaranteed to maintain grid safety. There are many advantages for this approach, such as large improvements in the speed of verification, as well as valuable information for design placement and floorplanning regarding the locations on the chip where high power blocks may be placed.