Computer-Aided Design for High-Performance Large-Scale Integrated Circuits

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With the deployment of electronics across the modern economy, there is a need to ensure the reliability of electronic devices and systems in a wide range of sectors. Integrated Circuits (ICs, or simply "chips") are subject to degradation and aging due to a number of failure mechanisms that can lead to chip failure, possibly months or years after deployment. We focus specifically on electromigration (EM) in metal lines, a failure mechanism that causes metal lines on a chip to degrade and fail under high current density. The impact of EM has gotten worse with the shrinking dimensions of modern IC technology. My group develops computer-aided design (CAD) tools to ensure chip robustness in the face of EM degradation. Traditional methods of EM checking are based on empirical models and involve checking the current densities in metal lines against specifications that are technology-specific, rather than design-specific. These methods are easy to use and have served the industry well, but have become inadequate for modern IC technology. Among other things, a key failing of these methods is that they cannot track the movement of metal atoms across metal branches, leading to much reduced accuracy. In our previous work, we have developed an efficient approach for physics-based (rather than empirical) EM checking, based on simulation of the mechanical stress that develops in metal lines under high current density. This allows us to track the movement of metal atoms across different branches in large multi-branch metal structures, providing significant accuracy improvement. We have thus developed the first-ever EM stress simulator [IRPS-19], which was recognized with a Best Paper Award in ICCAD-2016. However, stress simulation is more time-consuming than a simple current density check, so more work is required before these advances can be transferred to the industry. This project aims to address this need, with a key innovative approach for current constraints generation. This would involve formulating and solving the inverse of the stress simulation problem, and promises to deliver high-impact solutions to both the research community and the industry. In the simulation approach, a simulator takes in the given input current specifications and provides the mechanical stress over time. Instead, given a safety limit on the stress everywhere in a metal network, we propose to generate constraints on the branch currents which, if guaranteed by design, would ensure that the stress remains safe during the specified chip lifetime. One can then simply check during design if the branch current densities satisfy the generated current constraints. The overall approach would effectively translate the EM lifetime specification into a specification of branch current constraints that are both technology and design specific. It would combine the accuracy of stress-based analysis with the speed and simplicity of a current density check; it would be the best of both worlds.