Fully ballance coded transmission for high-speed inter- and intra-chip data communication **

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Ultra-high speed inter-chip and intra-chip communications have created new communication challenges. To achieve the required throughput per area (chip area), designers are considering non-binary modulations, faster transmission or increasing the number of inter-circuit communication links (buses) which simultaneously transfer data. All these solutions make links more vulnerable to the existing diverse noises such as crosstalk, dispersion, reflection, and common-mode noises. Suggested solutions significantly increase the power consumption in the chip because they result in higher detection complexity, higher resource allocation, and power consumption. **Recently, forward error correction (FEC) coding is considered as a promising solution. However, existing FECs are not designed for the challenging problem of inter-chip communications and its severe constraints. Considering these constraints, in this work, we introduce a new concept that we refer to as fully-balanced coded transmission (FBCT) in which half of the links transfer (+1) and the other half transfer (-1). While FBCT has the potential to significantly reduce existing noises in inter-chip communications, it brings about new challenges. In particular, as discussed FBCT is by nature based on non-linear FECs. Hence, we need to tackle some challenging problems. First, non-linear codes are not studied extensively in the literature. Second, the balanced nature of the code, i.e., having the same number of zeroes and ones (-1 and +1 when modulated) is a new constraint, not considered ever before. Optimizing the code, mapping the information blocks to codewords, and optimally and efficiently decoding the code are all challenges to be handled in this project.**