CAD Tools for Multi/Many-core NoC and Heterogeneous Computing System Design

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A significant number of high performance (embedded)*computer systems are based on multi/many-core architectures and their*applications range from sophisticated aircraft or spacecraft flight control to*smart and ultra-mobile systems. With the continued device scaling as predicted*by Moore's Law, it is not possible for the computer architects to build faster single*processor systems due to high power consumption and architectural*limitations. To achieve higher performance, computer*architects are accommodating many heterogeneous cores including GPUs (Graphics*Processing Units) on a chip. Recent developments in the computing system design*have enabled the researchers to improve system performance by increasing the number*of cores while keeping a check on the power consumption. The number of cores in these systems are rising dramatically. GPUs were originally intended for graphics processing; however, they*are being used for a wide range of computation and data-intensive applications.*Such innovative usage trend has led the GPU manufacturers to modify the*GPU architecture from purely SIMD to hybrid SIMT (Single Instruction*Multiple Threads). Heterogeneous computing involving*CPU-GPU clusters for a System-on-Chip (SoC) is getting popular for high-end embedded applications.*** *We intend to investigate latest trends in single chip*CPU-GPU integration and architectures as well as challenges related to task mapping and scheduling for these systems. One of the main problems associated with the implementation*of embedded application on CPU-GPU systems is the high-power consumption*associated with GPUs. We propose to investigate state of the art task scheduling and*mapping techniques to minimize power consumption. We intend to*design application partitioning and allocation techniques for*CPU-GPU based heterogeneous systems consuming minimal power. On-line task mapping and scheduling techniques will also be developed for CPU-GPU based SoCs.*** We have been*investigating co-synthesis approaches for NoC (Network-on-Chip) based multi/many-core SoCs.*On-chip communication architecture plays a crucial role to optimize the power*and performance of many-core systems. Several challenges exist to extract*high performance from the multi-core system applications such as communication,*synchronization and exploiting parallelism. Our recent research has produced high*impact NoC router architectures and communication-aware core-graph mapping techniques. Most of the existing NoC design tools are either related*to application mapping to a regular topology or provide an optimal NoC*topology. We will address several additional and important aspects such*as NoC synthesis, communication architecture design and verification of multi/many-core*systems. We propose to investigate software (CAD) tools to design optimal NoCs by considering chip area, power and performance parameters. A novel and hybrid*optimization methodology will be formulated for NoC synthesis.