Embedded Supercomputing with Reconfigurable Hardware

我们使用计算的方式以及它如何影响我们的生活随着我们的技术能力而不断发展。高性能计算现在可以在比智能手机更小的设备中使用。 “物联网”是“将设备插入网络”的绰号，以便我们可以查询和改变它们的状态。在许多情况下，这也假设它们具有一定的自主处理能力。只要能源、网络带宽和响应延迟要求需要，重要的处理就可以直接在终端设备上完成。然而，当网络能量低于计算能量和/或可以使用专用加速器更快地计算结果时，专门的计算任务通常会被卸载到云端。***本研究旨在通过使用称为现场可编程门阵列 (FPGA) 的可重新配置硬件设备来提高独立嵌入式设备和嵌入数据中心的处理速度和能量。 FPGA是一种高容量可编程逻辑芯片，能够实现任何用户设计的数字电路，包括大规模并行计算系统。现代 FPGA 可以托管数百到数千个处理器内核，并实现超过 10 TeraFLOP 的性能。尽管具有巨大的性能潜力，最终用户对 FPGA 进行编程仍然极其困难。***为了克服 FPGA 难以编程的名声，研究人员发明了覆盖架构的概念，或者简称为覆盖。简单来说，覆盖层由两部分组成：(1) 架构，它是映射到 FPGA 的预先设计的并行计算机系统，以及 (2) 一组类似编译器的 CAD 工具。覆盖架构通常用 VHDL 或 Verilog 描述，并用于配置 FPGA。然而，覆盖架构无法解决任何问题，因为像任何计算机系统一样，它需要一个“程序”来运行。因此，需要类似编译器的 CAD 工具将用户的程序映射到覆盖架构中。这些类似编译器的 CAD 工具非常易于使用，与常规 CPU 的传统 C 编译器非常相似。因此，叠加将 FPGA 从难以编程的设备转变为非常易于编程的定制设计计算机系统。这使得最终用户可以获得 FPGA 的 TeraFLOPS 性能水平。***本提案中描述的研究涉及创建新的覆盖架构、用于将用户应用映射到覆盖的新工具以及用于将覆盖映射到 FPGA 设备本身的新工具。这将为图像处理、计算机视觉、机器学习、医疗诊断和软件定义无线电等重要的现代应用带来新的性能水平和新功能。**

The way in which we use computing and how it influences our lives continues to evolve with our technological capability. High-performance computing is now available in devices smaller than our smartphones. The “Internet of Things” is a moniker for “plugging devices” into the network so that we may query and alter their state. In many cases, this also presumes they have some autonomous processing capability. Significant processing can be done directly on the end device whenever the energy, network bandwidth and response latency requirements demand it. However, specialized compute tasks are often offloaded to the cloud, when network the energy is lower than the compute energy and/or the result can be computed faster using dedicated accelerators.***This research aims to improve processing speed and energy in standalone embedded devices and embedded in datacenters through the use of reconfigurable hardware devices known as Field-Programmable Gate Arrays (FPGAs). An FPGA is a high-capacity programmable logic chip, capable of implementing any user-designed digital circuit, including massively parallel computational systems. Modern FPGAs can host hundreds to thousands of processor cores and achieve more than 10 TeraFLOPs of performance. Despite this great performance potential, FPGAs remain extremely difficult to program by end users.***To overcome the difficult-to-program reputation of FPGAs, researchers have invented the notion of overlay architectures, or simply overlays. In simple terms, an overlay is two parts: (1) an architecture, which is a predesigned parallel computer system mapped into an FPGA, and (2) a set of compiler-like CAD tools. An overlay architecture is usually described in VHDL or Verilog, and used to configure the FPGA. However, an overlay architecture cannot solve any problems because, like any computer system, it needs a “program” to run. Hence, compiler-like CAD tools are needed to map a user's program into the overlay architecture. These compiler-like CAD tools are very easy to use, being much like traditional C compilers for regular CPUs. As a result, overlays transform an FPGA from a difficult-to-program device into a custom-designed computer system that is very easy to program. This makes the TeraFLOPS level of performance in FPGAs accessible to end-users.***The research described in this proposal involves the creation of new overlay architectures, new tools for mapping user applications into the overlays, and new tools for mapping overlays into FPGA devices themselves. This will enable new levels of performance and new capabilities for important modern applications such as image processing, computer vision, machine learning, medical diagnostics, and software-defined radio.**